VLSI Architectures for Modern Error-Correcting Codes

9

Non-binary LDPC decoder architectures

CONTENTS

9.1 Non-binary LDPC codes and decoding algorithms

9.1.1 Belief propagation decoding algorithms

9.1.1.1 Frequency-domain decoding algorithm

9.1.1.2 Log-domain decoding algorithm

9.1.1.3 Mixed-domain decoding algorithm

9.1.2 Extended Min-sum and Min-max algorithms

9.1.3 Iterative reliability-based majority-logic decoding

9.2 Min-max decoder architectures

9.2.1 Forward-backward Min-max check node processing

9.2.1.1 Elementary step architecture with all q messages and polynomial representation

9.2.1.2 Elementary step architecture with all q messages and power representation

9.2.1.3 Elementary step architecture with < q messages

9.2.1.4 Scheduling of elementary steps

9.2.2 Trellis-based path-construction ...