Three-Dimensional Integrated Circuit Design, 2nd Edition

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This model of skew variations is used to analyze the effects of process variations on various 3-D clock trees. This model is extended to include variations of the horizontal interconnects, as described in Appendix F.

The accuracy of the model is demonstrated through a comparison with Monte Carlo simulations. The structure used for this purpose is an H-tree clock distribution network. This H-tree is placed in a circuit with a total area of 10 mm×10 mm. The circuit is assumed to be manufactured in a 45 nm CMOS technology. The parameters of the transistors and the interconnects are extracted from the PTM 45 nm CMOS and global interconnect ...