Three-Dimensional Integrated Circuit Design, 2nd Edition

Appendix F

Extension of the Proposed Model to Include Variations of Wires

The model described in Section 17.2 can be extended to include variations in the horizontal wires. This extended model is presented in this appendix. Consider the 3-D clock tree shown in Fig. 17.8, where the delay variations of a buffer stage Δd_stage(i) include the variations due to the capacitance ΔC_int and resistance ΔR_int of the wires,

$\begin{array}{ll}\mathrm{\Delta }{d}_{\mathrm{stage}(i)}\hfill & =\mathrm{\Delta }{d}_i+0.69\left({R\prime }_{b(i)}+\mathrm{\Delta }{R}_{b(i)}\right)\mathrm{\Delta }{C}_{\mathrm{int}}+0.38\left({R\prime }_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}\right)\\ +0.69\left({R\prime }_{\mathrm{int}}\mathrm{\Delta }{C}_{b(i+1)}+\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{b(i+1)}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{b(i+1)}\right).\hfill \end{array}$ (F.1)

(F.1)

According to the definition of $\mathrm{\Delta }{d}_i$ in (17.24), the term $0.69{R\prime }_{\mathrm{int}}\left(\mathrm{\Delta }{C}_{b\left(i+1\right)}\right)$ is included in Δd_i