Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

7

Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects

K. Goel Sandeep and Devta-Prasanna Narendra

7.1 Introduction

7.2 Fault Set for Timing-Aware ATPG

7.3 Small-Delay Defect Pattern Generation

7.3.1 Approach 1: TDF plus Top-off SDD

7.3.2 Approach 2: Top-off SDD plus Top-off TDF

7.4 Experimental Results

7.5 Conclusion

References

7.1 Introduction

Advances in design methods and process technologies are causing a continuous increase in the complexity of integrated circuits (ICs). The increased complexity and nanometer feature sizes of modern ICs make them susceptible not only to manufacturing defects but also to performance and quality issues. Process variation, power supply noise, cross talk, resistive opens/bridges, and ...