Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

6

Output Deviations-Based SDD Testing

Yilmaz Mahmut

6.1 Introduction

6.2 The Need for Alternative Methods

6.3 Probabilistic Delay Fault Model and Output Deviations for SDDs

6.3.1 Method of Output Deviations

6.3.1.1 Gate Delay Defect Probabilities

6.3.1.2 Propagation of Signal Transition Probabilities

6.3.1.3 Implementation of Algorithm for Propagating Signal Transition Probabilities

6.3.1.4 Pattern-Selection Method

6.3.2 Practical Aspects and Adaptation to Industrial Circuits

6.3.3 Comparison to SSTA-Based Techniques

6.4 Simulation Results

6.4.1 Experimental Setup and Benchmarks

6.4.2 Simulation Results

6.4.3 Comparison of the Original Method to the Modified Method

6.5 Conclusions

6.6 Acknowledgments

References

6.1 Introduction

Very deep-submicron ...