Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

5

Circuit Path Grading Considering Layout, Process Variations, and Cross Talk

Peng Ke, Yilmaz Mahmut and Tehranipoor Mohammad

5.1 Introduction

5.1.1 Commercial Methodologies for SDD Detection

5.1.2 Academic Proposals for SDD Detection

5.2 Analyzing SDDs Induced by Variations

5.2.1 Impact of Process Variations on Path Delay

5.2.2 Impact of Cross Talk on Path Delay

5.3 TDF Pattern Evaluation and Selection

5.3.1 Path PDF Analysis

5.3.2 Pattern Selection

5.4 Experimental Results and Analysis

5.4.1 Pattern Selection Efficiency Analysis

5.4.2 Pattern Set Analysis

5.4.3 Long-Path Threshold Analysis

5.4.4 CPU Run Time Analysis

5.5 Conclusion

5.6 Acknowledgment

References

5.1 Introduction

The semiconductor industry has come to rely heavily on delay ...