Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

3

Timing-Aware ATPG

Kassab Mark, Nadeau-Dostie Benoit and Lin Xijiang

CONTENTS

3.1 Introduction

3.2 Delay Calculation and Quality Metrics

3.2.1 Delay Calculation

3.2.2 Delay Test Quality Metrics

3.2.2.1 Delay Test Coverage

3.2.2.2 Delay Test Quality Coverage

3.2.2.3 Statistical Delay Quality Level

3.3 Deterministic Test Generation

3.3.1 Test Generation with Timing Data

3.3.2 Fault Simulation with Timing Data

3.4 Trade-off between Test Quality and Test Cost

3.4.1 Dropping Based on Slack Margin

3.4.2 Timing-Critical Faults

3.5 Experimental Results

References

3.1 Introduction

With fabrication processes moving well below 90 nm, manufactured devices are increasingly vulnerable to timing-related defects caused by resistive shorts or resistive ...