Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

2

K Longest Paths

Duncan M. (Hank) Walker

CONTENTS

2.1 Introduction

2.2 Path Generation for Combinational Circuits

2.2.1 Refined Implicit False Path Elimination

2.3 Experimental Results for Combinational Circuits

2.4 Extension to Scan-Based At-Speed Testing of Sequential Circuits

2.5 Path Generation for Scan Circuits

2.5.1 Implications on Scanned Flip-Flops

2.5.2 Constraints from Nonscanned Memories

2.5.3 Final Justification

2.6 Experimental Results on Scan Circuits

2.6.1 Robust Test

2.6.2 Comparison to Transition Fault Tests

2.7 Conclusions

References

2.1 Introduction

Delay testing detects small manufacturing defects that do not cause functional failure but affect the speed of integrated circuits. The path delay fault model [Smith 1985] ...