Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

1

Fundamentals of Small-Delay Defect Testing

M. Reddy Sudhakar and Maxwell Peter

CONTENTS

1.1 Introduction

1.2 Trends and Challenges in Semiconductor Manufacturing

1.2.1 Process Complexity

1.2.2 Process Variability

1.2.3 Random versus Systematic Defects

1.2.4 Implications of Power and Timing Optimization

1.2.5 The Interaction of Yield, Quality, and Fault Coverage

1.3 Existing Test Methods and Challenges of Smaller Geometries

1.3.1 Line Stuck-at Fault Model

1.3.2 Bridging Fault Models

1.3.3 n-Detection

1.3.4 Transition Fault Model

1.3.5 Path Delay Fault Model

1.3.6 Test Implementation and Adaptive Test

1.4 Effect of Small Delays on Transition Testing

References

1.1 Introduction

Test of very large scale integration (VLSI) devices is essential ...