Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

5.5 CMOS LOGIC GATES

Here we are going to use CMOS transistors, known as complementary MOS transistors, consisting of both PMOS and NMOS transistors. As for NMOS logic circuits, these CMOS logic circuits have pull-up and pull-down networks. However, for CMOS logic, the pull-up network consists of PMOS transistors. The functions realized by pull-up and pull-down networks are complementary to each other. The n-channel network is between the output and ground, and the p-channel network is between the output and V_DD. The number of transistors in each network is equal to the number of inputs.

Figure 5.6 NMOS (Two-Input) NOR Gate and Its Truth Table

Figure 5.7 CMOS NOT Gate and Its Truth Table

5.5.1 CMOS Inverter

The circuit diagram for a CMOS inverter is shown in Figure 5.7. For the logic high input, transistor T₁ will be turned on and T₂ will be off, thus pulling down the output node to ground, resulting in logic 0 at the output. On the other hand, for logic 0 input, T₁ will be off and T₂ will be on, thus connecting the output node to the higher voltage, V_DD. Notice that there is no protective resistance.

5.5.2 CMOS NAND Gate

A CMOS (two-input) NAND gate is shown in Figure 5.8. For this network, if all the inputs are high, the NMOS transistors will be on, the PMOS transistors will be ...