Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

4.9 VHDL SIGNAL AND GENERATE STATEMENTS

4.9.1 Signal Statement

Signal is a VHDL keyword. It declares a signal of specified data type. A signal declaration is used to represent internal signals within an architecture declaration.

Figure 4.20 Logic Circuit with Internal Signals

Unlike entity ports, internal signals do not have a direction. Signal assignment statements execute only when the associated signals (appearing on the right-hand side of the assignment statement) change values. In VHDL, the order of concurrent statements in VHDL code does not affect the order in which the statements are executed. Signal assignments are concurrent and could execute in parallel fashion. Consider the logic circuit in Figure 4.20 where the internal signals are identified. Notice, that from the point of view of an entity declaration, the signals Sig₁, Sig₂, and Sig₃ are internal signals. They are neither input ports nor output ports, and therefore do not have a direction.

The VHDL program in Figure 4.21 implements the logic circuit in Figure 4.20. The entity declaration is similar to that in the VHDL program of Figure 4.6. The architecture declaration has been modified to include the internal signals. The logic function of the circuit is described in an indirect way using the internal signals. Both VHDL implementations (Figures 4.6 and 4.21) have the same logic function and should yield the same ...