Compact MOSFET Models for VLSI Design

5

The Scaled MOS Transistor

5.1 Introduction

The MOS transistor feature size has been subjected to scaling down for the last several decades [1–4, 6]. The scaling phenomenon has more or less followed the prediction of Moore's Law, according to which the complexity of MOS device integration is approximately doubled every eighteen months [4]. The extraordinary success in scaling or miniaturization of the feature size of MOS transistors is attributed to the following factors [4]

• High level of component integration (large scale) with the prospect of realizing a complete functional electronics subsystem/system on silicon, which improves system reliability.
• Cost reduction due to increased device and subsystem count in a given area of silicon estate, as chip area is directly related to minimum feature size.
• Short transit time of carrier in the channel and faster speed of charging and discharging of capacitive loads. The maximum clock frequency in a digital system is governed by the current drive and capacitive load, which improves with scaling.

Figure 5.1 shows the cross-section of a reference long channel MOS transistor and its scaled version. The long or scaled (short) MOSFET classification is broadly based on the relation of the channel length to the depletion widths under the gate for V_DS ≈ 0. When the channel length is considerably larger than the sum of the source and drain depletion widths, the transistor is considered to be long. The characteristics of a scaled MOS transistor ...