CMOS Analog Integrated Circuits

5.6.3    Optimization of a two-pole amplifier for fast settling response

Amplifiers used in high-speed applications should preferably be designed to achieve the minimum settling time [45,46]. In general, the settling time, t_s, is defined as the time required for the amplifier output voltage to settle to within an error tolerance, ∈, around the final steady-state value.

Consider a two-stage amplifier characterized by an open-loop transfer function of the form

$A\left(s\right)\frac{A_0}{\left(1-s/{\omega }_{p1}\right)\left(1-s/{\omega }_{p2}\right)},$

(5.431)

where A₀ is the dc gain, and ω_p1 and ω_p2 are the frequency locations of the first and second poles (p₁ and p₂), respectively. In a unity-gain configuration, the closed-loop transfer function is

FIGURE 5.63Step responses of a two-stage amplifier.