Advanced Frequency Synthesis by Phase Lock

APPENDIX H

SAMPLE-AND-HOLD CIRCUIT

Here we will look at the transient performance of the sample-and-hold circuits shown in Figs. 2.5 and 2.23 and of a modification of the former and we will consider the requirement for a capacitor between the charge pump and sampler.

We will find that the circuit in Fig. 2.5 has problems when the synthesizer steps down in frequency, especially for large steps. For this reason, we have added an inhibit to the circuit that is shown in the literature [Liu and Li, 2005; Cassia et al., 2003] to enable the sampling function to be overridden during frequency switching (acquisition). We will see that the ideal S&H circuit in Fig. 2.23 does not exhibit these problems and that the circuit of Fig. 2.5 can be used as a practical implementation of the S&H with a slight modification to its control signals.

H.1   TRANSIENT PERFORMANCE

We will compare the performance of these circuits in the synthesizer described in Fig. F.10.12, where simulation results from the MATLAB script SynCP.m are shown. The parameters given there are as follows:

The loop filter has a pole at 1 kHz and a zero at 100 Hz. There is another pole at 0.001 Hz, but we will vary that very low-frequency pole to suit our circuits while maintaining the same gain above 1 Hz.

H.1.1   No Sampling

The response without a sampler (with the switch in Fig. 2.23 bypassing the sampler) is shown in Fig. H.1 ...