Advanced Frequency Synthesis by Phase Lock

CHAPTER 2

FRACTIONAL-N AND BASIC ΣΔ SYNTHESIZERS

Following are some of the reasons for using a fractional-N synthesizer (Section F.8.3):

• to obtain fine resolution (step size) while maintaining a wide bandwidth for switching speed or suppression of VCO phase noise;
• to obtain fine resolution without the analog circuitry required for multiple loops;
• to minimize the divide ratio N in order to not multiply the reference phase noise by a larger number; and
• to obtain rapid phase-continuous switching for frequency sweeping.

In the fractional-N synthesizer, the divide number is changed periodically; so the average synthesized frequency is between values that could be obtained with integer N. The sequence of divide numbers is typically controlled by an accumulator that periodically produces an output to alter the value of N. Here is a simple example.

2.1   FIRST-ORDER FRACTIONAL-N

Suppose that the effective value of N is to be 10.125, that is, 10 and 1/8. Then N will be 11 for 1 out of 8 reference periods and 10 for the other 7. This can be done by accumulating the number 1/8—adding it to an existing value each reference period—and using the carry (overflow) output to increase N from 10 to 11. Table 2.1 shows the repeated sequence (the first row occurs again after the last row) of binary fractions that results from accumulating the fraction 1/8 = 0.125_d = 0.001_b.

TABLE 2.1   Accumulator Contents with 1/8 Input

The accumulator (Fig. 2.1 and Appendix C) might consist of a 3-bit register ...