Advanced Frequency Synthesis by Phase Lock

APPENDIX C

FRACTIONAL CANCELLATION

In this appendix, we show how the accumulator contents in a simple (composed of first-order stages) MASH modulator are related to the phase error and can, therefore, be used to compensate it. Numbers will be normalized to the capacity of the accumulator, which will, therefore, equal 1.

C.1   MODULATOR DETAILS

Let us consider the implementation of the modulator in Fig. 2.1 in more detail. Figure C.1 shows the general concept of a first-order MASH modulator. The input is a binary fraction. An accumulator drives a quantizer and the quantizer output is fed back to subtract 1 from the input. A possible implementation is shown in Fig. C.2. Here, only 4 bits are shown for simplicity in the drawing. Many more bits are usual in practice, but the concepts remain the same. There is a storage register to store the previous output and probably also an input register, although it is sometimes simpler to consider the realization without one, as is done in Section F.8.3.5. Here, we will concentrate on the accumulator with an input register.

Shortly after the clock causes the registers to be updated, the arithmetic sum of the input and the previous output appear at the output. The n (=4) least significant bits at the output are sent to the storage register. The most significant bit becomes the output of the quantizer, Q_out. The process of subtracting 1 from the input occurs automatically as the n-bit number at a rolls over (i.e., the sum becomes greater than ...