"I would like to thank the inventor of Ethernet"

is correct.

Should _not_ read "inventors"

Source: Packet Communication, 1996, Robert M. Metcalfe. 185pp. peer-to-peer.com ISBN 15739-80331 TK5105.3M48 1996

10BASE2 is listed here as 802.3a-1985 and in 802.3, 2000 Edition, as 802.3a-
1988." Which date is correct?

FOIRL is listed here as being published in 1989 but in 802.3, 2000 Edition, as
802.3d-1987. Which date is correct?

You describe the drawback to Manchester encoding as:

"In other words, a 10 Mbps stream of all ones or all zeroes results in a Manchester
encoded signaling rate of 20 MHz on the cable."

This passage seems to indicate that a stream of all ones or all zeroes results in a
20 MHz signal on the media. If this is the case, I believe this statement is wrong.

The stream of all ones or all zeroes would be represented by a 10 MHz square wave
signal. A stream of alternating ones and zeroes (good case) would be represented by
a 5 MHz square wave signal. This suggest a minimum signal frequency of 5 MHz and a
maximum frequency of 10 MHz on the cable using the Manchester encoding scheme.

When a Manchester encoding scheme is used, half the bandwidth is wasted because it
takes two transitions to represent one bit. This is something you may wish to state
in the book. To see this, consider a original clock signal and a data signal
representation. If this was your interface, the clock would be a 10 MHz signal and
the data signal would never be higher than 5 MHz (alternating ones and zeroes). When
this is converted to a Manchester encoding scheme, the Manchester signal line
represents the alternating ones and zeroes as a 5 MHz signal, thus no change.
However, the stream of all ones or all zeroes results in a 10 MHz signal, a big
change. Thus the Manchester encoding scheme caused a data line that never went
higher than 5 MHz to be represented by a new signal line that will never go higher
than 10 MHz. Thus double frequency representation.

If you look at figure 6-8 on page 119, this figure supports my argument. On the 001
pattern, the time between the first zeroes represented by rising edge signals is 100
nsec. This suggest a 100 nsec time period thus 10 MHz.

Sorry to be so anile, but I thought this was an important point.

The Cisco catalyst 3500 XL switch appears to make use of a proprietary two
port repeater built into a copper GBIC. This allows daisy chaining several
switches using 1000-BASE-?? 1/2 duplex mode of operation. The interconnect
cable may be proprietary. From the Cisco web site:

GigaStack GBIC delivers a low-cost, independent stack bus with a 1 Gbps
forwarding bandwidth in a daisy-chain configuration, with up to nine
Catalyst 3500 XL or gigabit-enabled Catalyst 2900 series XL switches or a 2
Gbps forwarding rate in a point-to-point configuration

Considering the margin of 0 to 5 bits, round to the nearest bit.

Segment Round-Trip Delay Values in Bit Times

Left Middle Right RT
Max End Segment End Delay/
Segment Length
Type (m) Base Max Base Max Base Max meter v/c
____________________________________________________________________
10BASE-FL 2000 12 212 34 234 157 357 .100 .667
FOIRL 1000 8 108 29 129 152 252 .100 .667
10BASE5 500 12 55 47 90 170 213 .087 .770
10BASE2 185 12 31 47 65 170 188 .103 .650
10BASE-T 100 15 27 42 53 165 176 .114 .585
Excess AUI 48 0 5 0 5 0 5 .103 .650

RT delay/m (100.ns bit times/m) = 2 / [(v/c)*(30.0 m/100.ns)]

Include the right-hand column and that last equation to help readers compute
their own. Listing longest-to-shortest as above helps keep the numbers in
perspective. This table is comprehensible and useful. The original's
appearance warns, "Don't go here."

For left and right ends, tabulate only _excess_ delay beyond the minima
(7.75 and 152 bit times, respectively). Maximum allowed path excess delay
becomes 415 bit times (preferably 410). The comparison of left- to right-
direction paths becomes far easier! (Try it.) Round to 0 decimal point;
align on decimal. List longest-to-shortest. Say "N/A" for "Excess AUI Base."

Segment Excess Delay Values (bit times)
RT max. network diameter
Segment Left End Mid R. End delay including AUI (m)
Type Base Max B. Max B. Max /m v/c (if net all same type)
10BASE-F 5 205 34 234 5 205 .1 .667 4008
FOIRL 0 100 29 129 0 100 .1 .667 3588
10BASE5 4 47 47 90 18 61 .0866 .77 2888
10BASE2 4 23 47 65 18 36 .103 .65 1425
10BASE-T 8 19 42 53 13 24 .114 .585 1200
Excess AUI N/A 5 NA 5 NA 5 .103 .65 N/A

This is possible because every multisegment path has at least a left end and
a right end, with or without mid segments.

It's worth mentioning that _no_ 10Mb/s network shorter than 2700 meters
(including AUI) is delay-limited!! So for networks shorter than that, this
exercise can be skipped!!! That includes _all_ purely 10BASE-T and 10BASE2
networks. Open the section with that observation.

"IEEE uses _c_ = 3.00 * 10^8 for Ethernet calculations."