VLSI Test Principles and Architectures

VLSI Test Principles and Architectures

by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Khader S. Abdel-Hafez, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C.-M. Li, Mike Peng Li, Xiaowei Li, T.M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Soumendu Bhattacharya, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Erik H. Volkerink, Duncan Walker, Shianling Wu, Nur A. Touba, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting Cheng, William Eklow, Michael S. Hsiao, Jiun-Lang Huang, Shi-Yu Huang
Released August 2006
Publisher(s): Morgan Kaufmann
ISBN: 9780080474793

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Book description

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
  • Most up-to-date coverage of design for testability.
  • Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
  • Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Table of contents

  1. Copyright
  2. In Praise of VLSI Test Principles and Architectures: Design for Testability
  3. The Morgan Kaufmann Series in Systems on Silicon
  4. Preface
  5. In the Classroom
  6. Acknowledgments
  7. Contributors
  8. About the Editors
  9. 1. Introduction
    1. About this Chapter
    2. 1.1. Importance of Testing
    3. 1.2. Testing During the VLSI Lifecycle
      1. 1.2.1. VLSI Development Process
        1. 1.2.1.1. Design Verification
        2. 1.2.1.2. Yield and Reject Rate
      2. 1.2.2. Electronic System Manufacturing Process
      3. 1.2.3. System-Level Operation
    4. 1.3. Challenges in VLSI Testing
      1. 1.3.1. Test Generation
      2. 1.3.2. Fault Models
        1. 1.3.2.1. Stuck-At Faults
        2. 1.3.2.2. Transistor Faults
        3. 1.3.2.3. Open and Short Faults
        4. 1.3.2.4. Delay Faults and Crosstalk
        5. 1.3.2.5. Pattern Sensitivity and Coupling Faults
        6. 1.3.2.6. Analog Fault Models
    5. 1.4. Levels of Abstraction in VLSI Testing
      1. 1.4.1. Register-Transfer Level and Behavioral Level
      2. 1.4.2. Gate Level
      3. 1.4.3. Switch Level
      4. 1.4.4. Physical Level
    6. 1.5. Historical Review of VLSI Test Technology
      1. 1.5.1. Automatic Test Equipment
      2. 1.5.2. Automatic Test Pattern Generation
      3. 1.5.3. Fault Simulation
      4. 1.5.4. Digital Circuit Testing
      5. 1.5.5. Analog and Mixed-Signal Circuit Testing
      6. 1.5.6. Design for Testability
      7. 1.5.7. Board Testing
      8. 1.5.8. Boundary Scan Testing
    7. 1.6. Concluding Remarks
    8. 1.7. Exercises
    9. Acknowledgments
    10. References
        1. R1.0—Books
        2. R1.1—Importance of Testing
        3. R1.3—Challenges in VLSI Testing
        4. R1.4—Levels of Abstraction in VLSI Testing
        5. R1.5—Historical Review of VLSI Test Technology
  10. 2. Design for Testability
    1. About this Chapter
    2. 2.1. Introduction
    3. 2.2. Testability Analysis
      1. 2.2.1. SCOAP Testability Analysis
        1. 2.2.1.1. Combinational Controllability and Observability Calculation
        2. 2.2.1.2. Sequential Controllability and Observability Calculation
      2. 2.2.2. Probability-Based Testability Analysis
      3. 2.2.3. Simulation-Based Testability Analysis
      4. 2.2.4. RTL Testability Analysis
    4. 2.3. Design for Testability Basics
      1. 2.3.1. Ad Hoc Approach
        1. 2.3.1.1. Test Point Insertion
      2. 2.3.2. Structured Approach
    5. 2.4. Scan Cell Designs
      1. 2.4.1. Muxed-D Scan Cell
      2. 2.4.2. Clocked-Scan Cell
      3. 2.4.3. LSSD Scan Cell
    6. 2.5. Scan Architectures
      1. 2.5.1. Full-Scan Design
        1. 2.5.1.1. Muxed-D Full-Scan Design
        2. 2.5.1.2. Clocked Full-Scan Design
        3. 2.5.1.3. LSSD Full-Scan Design
      2. 2.5.2. Partial-Scan Design
      3. 2.5.3. Random-Access Scan Design
    7. 2.6. Scan Design Rules
      1. 2.6.1. Tristate Buses
      2. 2.6.2. Bidirectional I/O Ports
      3. 2.6.3. Gated Clocks
      4. 2.6.4. Derived Clocks
      5. 2.6.5. Combinational Feedback Loops
      6. 2.6.6. Asynchronous Set/Reset Signals
    8. 2.7. Scan Design Flow
      1. 2.7.1. Scan Design Rule Checking and Repair
      2. 2.7.2. Scan Synthesis
        1. 2.7.2.1. Scan Configuration
        2. 2.7.2.2. Scan Replacement
        3. 2.7.2.3. Scan Reordering
        4. 2.7.2.4. Scan Stitching
      3. 2.7.3. Scan Extraction
      4. 2.7.4. Scan Verification
        1. 2.7.4.1. Verifying the Scan Shift Operation
        2. 2.7.4.2. Verifying the Scan Capture Operation
      5. 2.7.5. Scan Design Costs
    9. 2.8. Special-Purpose Scan Designs
      1. 2.8.1. Enhanced Scan
      2. 2.8.2. Snapshot Scan
      3. 2.8.3. Error-Resilient Scan
    10. 2.9. RTL Design for Testability
      1. 2.9.1. RTL Scan Design Rule Checking and Repair
      2. 2.9.2. RTL Scan Synthesis
      3. 2.9.3. RTL Scan Extraction and Scan Verification
    11. 2.10. Concluding Remarks
    12. 2.11. Exercises
    13. Acknowledgments
    14. References
        1. R2.0—Books
        2. R2.1—Introduction
        3. R2.2—Testability Analysis
        4. R2.3—Design for Testability Basics
        5. R2.4—Scan Cell Designs
        6. R2.5—Scan Architectures
        7. R2.6—Scan Design Rules
        8. R2.7—Scan Design Flow
        9. R2.8—Special-Purpose Scan Designs
        10. R2.9—RTL Design for Testability
        11. R2.10—Concluding Remarks
  11. 3. Logic and Fault Simulation
    1. About this Chapter
    2. 3.1. Introduction
      1. 3.1.1. Logic Simulation for Design Verification
      2. 3.1.2. Fault Simulation for Test and Diagnosis
    3. 3.2. Simulation Models
      1. 3.2.1. Gate-Level Network
        1. 3.2.1.1. Sequential Circuits
      2. 3.2.2. Logic Symbols
        1. 3.2.2.1. Unknown State u
        2. 3.2.2.2. High-Impedance State Z
        3. 3.2.2.3. Intermediate Logic States
      3. 3.2.3. Logic Element Evaluation
        1. 3.2.3.1. Truth Tables
        2. 3.2.3.2. Input Scanning
        3. 3.2.3.3. Input Counting
        4. 3.2.3.4. Parallel Gate Evaluation
      4. 3.2.4. Timing Models
        1. 3.2.4.1. Transport Delay
        2. 3.2.4.2. Inertial Delay
        3. 3.2.4.3. Wire Delay
        4. 3.2.4.4. Functional Element Delay Model
    4. 3.3. Logic Simulation
      1. 3.3.1. Compiled-Code Simulation
        1. 3.3.1.1. Logic Optimization
        2. 3.3.1.2. Logic Levelization
        3. 3.3.1.3. Code Generation
      2. 3.3.2. Event-Driven Simulation
        1. 3.3.2.1. Nominal-Delay Event-Driven Simulation
      3. 3.3.3. Compiled-Code versus Event-Driven Simulation
      4. 3.3.4. Hazards
        1. 3.3.4.1. Static Hazard Detection
        2. 3.3.4.2. Dynamic Hazard Detection
    5. 3.4. Fault Simulation
      1. 3.4.1. Serial Fault Simulation
      2. 3.4.2. Parallel Fault Simulation
        1. 3.4.2.1. Parallel Fault Simulation
        2. 3.4.2.2. Parallel-Pattern Fault Simulation
      3. 3.4.3. Deductive Fault Simulation
      4. 3.4.4. Concurrent Fault Simulation
      5. 3.4.5. Differential Fault Simulation
      6. 3.4.6. Fault Detection
      7. 3.4.7. Comparison of Fault Simulation Techniques
      8. 3.4.8. Alternatives to Fault Simulation
        1. 3.4.8.1. Toggle Coverage
        2. 3.4.8.2. Fault Sampling
        3. 3.4.8.3. Critical Path Tracing
        4. 3.4.8.4. Statistical Fault Analysis
    6. 3.5. Concluding Remarks
    7. 3.6. Exercises
    8. References
        1. R3.0—Books
        2. R3.1—Introduction
        3. R3.2—Simulation Models
        4. R3.3—Logic Simulation
        5. R3.4—Fault Simulation
        6. R3.5—Concluding Remarks
  12. 4. Test Generation
    1. About this Chapter
    2. 4.1. Introduction
    3. 4.2. Random Test Generation
      1. 4.2.1. Exhaustive Testing
    4. 4.3. Theoretical Background: Boolean Difference
      1. 4.3.1. Untestable Faults
    5. 4.4. Designing a Stuck-At ATPG for Combinational Circuits
      1. 4.4.1. A Naive ATPG Algorithm
        1. 4.4.1.1. Backtracking
      2. 4.4.2. A Basic ATPG Algorithm
      3. 4.4.3. D Algorithm
      4. 4.4.4. PODEM
      5. 4.4.5. FAN
      6. 4.4.6. Static Logic Implications
      7. 4.4.7. Dynamic Logic Implications
    6. 4.5. Designing a Sequential ATPG
      1. 4.5.1. Time Frame Expansion
      2. 4.5.2. 5-Valued Algebra Is Insufficient
      3. 4.5.3. Gated Clocks and Multiple Clocks
    7. 4.6. Untestable Fault Identification
      1. 4.6.1. Multiple-Line Conflict Analysis
    8. 4.7. Designing a Simulation-Based ATPG
      1. 4.7.1. Overview
      2. 4.7.2. Genetic-Algorithm-Based ATPG
        1. 4.7.2.1. Issues Concerning the GA Population
        2. 4.7.2.2. Issues Concerning GA Parameters
        3. 4.7.2.3. Issues Concerning the Fitness Function
        4. 4.7.2.4. CASE Studies
    9. 4.8. Advanced Simulation-Based ATPG
      1. 4.8.1. Seeding the GA with Helpful Sequences
      2. 4.8.2. Logic-Simulation-Based ATPG
      3. 4.8.3. Spectrum-Based ATPG
    10. 4.9. Hybrid Deterministic and Simulation-Based ATPG
      1. 4.9.1. ALT-TEST Hybrid
    11. 4.10. ATPG for Non-Stuck-At Faults
      1. 4.10.1. Designing an ATPG That Captures Delay Defects
        1. 4.10.1.1. Classification of Path-Delay Faults
        2. 4.10.1.2. ATPG for Path-Delay Faults
      2. 4.10.2. ATPG for Transition Faults
      3. 4.10.3. Transition ATPG Using Stuck-At ATPG
      4. 4.10.4. Transition ATPG Using Stuck-At Vectors
        1. 4.10.4.1. Transition Test Chains via Weighted Transition Graph
      5. 4.10.5. Bridging Fault ATPG
    12. 4.11. Other Topics in Test Generation
      1. 4.11.1. Test Set Compaction
      2. 4.11.2. N-Detect ATPG
      3. 4.11.3. ATPG for Acyclic Sequential Circuits
      4. 4.11.4. IDDQ Testing
      5. 4.11.5. Designing a High-Level ATPG
    13. 4.12. Concluding Remarks
    14. 4.13. Exercises
    15. References
        1. R4.1—Introduction
        2. R4.2—Random Test Generation
        3. R4.4—Designing a Stuck-At ATPG for Combinational Circuits
        4. R4.5—Designing a Sequential ATPG
        5. R4.6—Untestable Fault Identification
        6. R4.7—Designing a Simulation-Based ATPG
        7. R4.8—Advanced Simulation-Based ATPG
        8. R4.9—Hybrid Deterministic and Simulation-Based ATPG
        9. R4.10—ATPG for Non-Stuck-At Faults
        10. R4.11—Other Topics in Test Generation
  13. 5. Logic Built-In Self-Test
    1. About this Chapter
    2. 5.1. Introduction
    3. 5.2. BIST Design Rules
      1. 5.2.1. Unknown Source Blocking
        1. 5.2.1.1. Analog Blocks
        2. 5.2.1.2. Memories and Non-Scan Storage Elements
        3. 5.2.1.3. Combinational Feedback Loops
        4. 5.2.1.4. Asynchronous Set/Reset Signals
        5. 5.2.1.5. Tristate Buses
        6. 5.2.1.6. False Paths
        7. 5.2.1.7. Critical Paths
        8. 5.2.1.8. Multiple-Cycle Paths
        9. 5.2.1.9. Floating Ports
        10. 5.2.1.10. Bidirectional I/O Ports
      2. 5.2.2. Re-Timing
    4. 5.3. Test Pattern Generation
      1. 5.3.1. Exhaustive Testing
        1. 5.3.1.1. Binary Counter
        2. 5.3.1.2. Complete LFSR
      2. 5.3.2. Pseudo-Random Testing
        1. 5.3.2.1. Maximum-Length LFSR
        2. 5.3.2.2. Weighted LFSR
        3. 5.3.2.3. Cellular Automata
      3. 5.3.3. Pseudo-Exhaustive Testing
        1. 5.3.3.1. Verification Testing
          1. Syndrome Driver Counter
          2. Constant-Weight Counter
          3. Combined LFSR/SR
          4. Combined LFSR/PS
          5. Condensed LFSR
          6. Cyclic LFSR
          7. Compatible LFSR
        2. 5.3.3.2. Segmentation Testing
      4. 5.3.4. Delay Fault Testing
      5. 5.3.5. Summary
    5. 5.4. Output Response Analysis
      1. 5.4.1. Ones Count Testing
      2. 5.4.2. Transition Count Testing
      3. 5.4.3. Signature Analysis
        1. 5.4.3.1. Serial Signature Analysis
        2. 5.4.3.2. Parallel Signature Analysis
    6. 5.5. Logic BIST Architectures
      1. 5.5.1. BIST Architectures for Circuits without Scan Chains
        1. 5.5.1.1. A Centralized and Separate Board-Level BIST Architecture
        2. 5.5.1.2. Built-In Evaluation and Self-Test (BEST)
      2. 5.5.2. BIST Architectures for Circuits with Scan Chains
        1. 5.5.2.1. LSSD On-Chip Self-Test
        2. 5.5.2.2. Self-Testing Using MISR and Parallel SRSG
      3. 5.5.3. BIST Architectures Using Register Reconfiguration
        1. 5.5.3.1. Built-In Logic Block Observer
        2. 5.5.3.2. Modified Built-In Logic Block Observer
        3. 5.5.3.3. Concurrent Built-In Logic Block Observer
        4. 5.5.3.4. Circular Self-Test Path (CSTP)
      4. 5.5.4. BIST Architectures Using Concurrent Checking Circuits
        1. 5.5.4.1. Concurrent Self-Verification
      5. 5.5.5. Summary
    7. 5.6. Fault Coverage Enhancement
      1. 5.6.1. Test Point Insertion
        1. 5.6.1.1. Test Point Placement
        2. 5.6.1.2. Control Point Activation
      2. 5.6.2. Mixed-Mode BIST
        1. 5.6.2.1. ROM Compression
        2. 5.6.2.2. LFSR Reseeding
        3. 5.6.2.3. Embedding Deterministic Patterns
      3. 5.6.3. Hybrid BIST
    8. 5.7. BIST Timing Control
      1. 5.7.1. Single-Capture
        1. 5.7.1.1. One-Hot Single-Capture
        2. 5.7.1.2. Staggered Single-Capture
      2. 5.7.2. Skewed-Load
        1. 5.7.2.1. One-Hot Skewed-Load
        2. 5.7.2.2. Aligned Skewed-Load
        3. 5.7.2.3. Staggered Skewed-Load
      3. 5.7.3. Double-Capture
        1. 5.7.3.1. One-Hot Double-Capture
        2. 5.7.3.2. Aligned Double-Capture
        3. 5.7.3.3. Staggered Double-Capture
      4. 5.7.4. Fault Detection
    9. 5.8. A Design Practice
      1. 5.8.1. BIST Rule Checking and Violation Repair
      2. 5.8.2. Logic BIST System Design
        1. 5.8.2.1. Logic BIST Architecture
        2. 5.8.2.2. TPG and ORA
        3. 5.8.2.3. Test Controller
        4. 5.8.2.4. Clock Gating Block
        5. 5.8.2.5. Re-Timing Logic
        6. 5.8.2.6. Fault Coverage Enhancing Logic and Diagnostic Logic
      3. 5.8.3. RTL BIST Synthesis
      4. 5.8.4. Design Verification and Fault Coverage Enhancement
    10. 5.9. Concluding Remarks
    11. 5.10. Exercises
    12. Acknowledgments
    13. References
        1. R5.0—Books
        2. R5.2—BIST Design Rules
        3. R5.3—Test Pattern Generation
        4. R5.4—Output Response Analysis
        5. R5.5—Logic BIST Architectures
        6. R5.6—Fault Coverage Enhancement
        7. R5.7—BIST Timing Control
        8. R5.8—A Design Practice
        9. R5.9—Concluding Remarks
  14. 6. Test Compression
    1. About this Chapter
    2. 6.1. Introduction
    3. 6.2. Test Stimulus Compression
      1. 6.2.1. Code-Based Schemes
        1. 6.2.1.1. Dictionary Code (Fixed-to-Fixed)
        2. 6.2.1.2. Huffman Code (Fixed-to-Variable)
        3. 6.2.1.3. Run-Length Code (Variable-to-Fixed)
        4. 6.2.1.4. Golomb Code (Variable-to-Variable)
      2. 6.2.2. Linear-Decompression-Based Schemes
        1. 6.2.2.1. Combinational Linear Decompressors
        2. 6.2.2.2. Fixed-Length Sequential Linear Decompressors
        3. 6.2.2.3. Variable-Length Sequential Linear Decompressors
        4. 6.2.2.4. Combined Linear and Nonlinear Decompressors
      3. 6.2.3. Broadcast-Scan-Based Schemes
        1. 6.2.3.1. Broadcast Scan
        2. 6.2.3.2. Illinois Scan
        3. 6.2.3.3. Multiple-Input Broadcast Scan
        4. 6.2.3.4. Reconfigurable Broadcast Scan
        5. 6.2.3.5. Virtual Scan
    4. 6.3. Test Response Compaction
      1. 6.3.1. Space Compaction
        1. 6.3.1.1. Zero-Aliasing Linear Compaction
        2. 6.3.1.2. X-Compact
        3. 6.3.1.3. X-Blocking
        4. 6.3.1.4. X-Masking
        5. 6.3.1.5. X-Impact
      2. 6.3.2. Time Compaction
      3. 6.3.3. Mixed Time and Space Compaction
    5. 6.4. Industry Practices (Edited by Laung-Terng Wang)
      1. 6.4.1. OPMISR+
      2. 6.4.2. Embedded Deterministic Test
      3. 6.4.3. VirtualScan and UltraScan
      4. 6.4.4. Adaptive Scan
      5. 6.4.5. ETCompression
      6. 6.4.6. Summary
    6. 6.5. Concluding Remarks
    7. 6.6. Exercises
    8. Acknowledgments
    9. References
        1. R6.0—Books
        2. R6.1—Introduction
        3. R6.2—Test Stimulus Compression
        4. R6.3—Test Response Compaction
        5. R6.4—Industry Practices
  15. 7. Logic Diagnosis
    1. About this Chapter
    2. 7.1. Introduction
    3. 7.2. Combinational Logic Diagnosis
      1. 7.2.1. Cause–Effect Analysis
        1. 7.2.1.1. Compaction and Compression of Fault Dictionary
      2. 7.2.2. Effect–Cause Analysis
        1. 7.2.2.1. Structural Pruning
        2. 7.2.2.2. Backtrace Algorithm
        3. 7.2.2.3. Inject-and-Evaluate Paradigm
      3. 7.2.3. Chip-Level Strategy
        1. 7.2.3.1. Direct Partitioning
        2. 7.2.3.2. Two-Phase Strategy
        3. 7.2.3.3. Overall Chip-Level Diagnostic Flow
      4. 7.2.4. Diagnostic Test Pattern Generation
      5. 7.2.5. Summary of Combinational Logic Diagnosis
    4. 7.3. Scan Chain Diagnosis
      1. 7.3.1. Preliminaries for Scan Chain Diagnosis
      2. 7.3.2. Hardware-Assisted Method
      3. 7.3.3. Modified Inject-and-Evaluate Paradigm
      4. 7.3.4. Signal-Profiling-Based Method
        1. 7.3.4.1. Diagnostic Test Sequence Selection
        2. 7.3.4.2. Run-and-Scan Test Application
        3. 7.3.4.3. Why Functional Sequences?
        4. 7.3.4.4. Profiling-Based Analysis
      5. 7.3.5. Summary of Scan Chain Diagnosis
    5. 7.4. Logic BIST Diagnosis
      1. 7.4.1. Overview of Logic BIST Diagnosis
      2. 7.4.2. Interval-Based Methods
      3. 7.4.3. Masking-Based Methods
    6. 7.5. Concluding Remarks
    7. 7.6. Exercises
    8. Acknowledgments
    9. References
        1. R7.0—Books
        2. R7.1—Introduction
        3. R7.2—Combinational Logic Diagnosis
        4. R7.3—Scan Chain Diagnosis
        5. R7.4—Logic BIST Diagnosis
  16. 8. Memory Testing and Built-In Self-Test
    1. About this Chapter
    2. 8.1. Introduction
    3. 8.2. RAM Functional Fault Models and Test Algorithms
      1. 8.2.1. RAM Functional Fault Models
      2. 8.2.2. RAM Dynamic Faults
      3. 8.2.3. Functional Test Patterns and Algorithms
      4. 8.2.4. March Tests
      5. 8.2.5. Comparison of RAM Test Patterns
      6. 8.2.6. Word-Oriented Memory
      7. 8.2.7. Multi-Port Memory
    4. 8.3. RAM Fault Simulation and Test Algorithm Generation
      1. 8.3.1. Fault Simulation
      2. 8.3.2. RAMSES
      3. 8.3.3. Test Algorithm Generation by Simulation
    5. 8.4. Memory Built-In Self-Test
      1. 8.4.1. RAM Specification and BIST Design Strategy
      2. 8.4.2. BIST Architectures and Functions
      3. 8.4.3. BIST Implementation
      4. 8.4.4. BRAINS: A RAM BIST Compiler
    6. 8.5. Concluding Remarks
    7. 8.6. Exercises
    8. Acknowledgments
    9. References
        1. R8.1—Introduction
        2. R8.2—RAM Functional Fault Models and Test Algorithms
        3. R8.3—RAM Fault Simulation and Test Algorithm Generation
        4. R8.4—Memory Built-In Self-Test
  17. 9. Memory Diagnosis and Built-In Self-Repair
    1. About this Chapter
    2. 9.1. Introduction
      1. 9.1.1. Why Memory Diagnosis?
      2. 9.1.2. Why Memory Repair?
    3. 9.2. Refined Fault Models and Diagnostic Test Algorithms
    4. 9.3. BIST with Diagnostic Support
      1. 9.3.1. Controller
      2. 9.3.2. Test Pattern Generator
      3. 9.3.3. Fault Site Indicator (FSI)
    5. 9.4. RAM Defect Diagnosis and Failure Analysis
    6. 9.5. RAM Redundancy Analysis Algorithms
      1. 9.5.1. Conventional Redundancy Analysis Algorithms
      2. 9.5.2. The Essential Spare Pivoting Algorithm
      3. 9.5.3. Repair Rate and Overhead
    7. 9.6. Built-In Self-Repair
      1. 9.6.1. Redundancy Organization
      2. 9.6.2. BISR Architecture and Procedure
      3. 9.6.3. BIST Module
      4. 9.6.4. BIRA Module
      5. 9.6.5. An Industrial Case
      6. 9.6.6. Repair Rate and Yield
    8. 9.7. Concluding Remarks
    9. 9.8. Exercises
    10. Acknowledgments
    11. References
        1. R9.1—Introduction
        2. R9.2—Refined Fault Models and Diagnostic Test Algorithms
        3. R9.3—BIST with Diagnostic Support
        4. R9.4—RAM Defect Diagnosis and Failure Analysis
        5. R9.5—RAM Redundancy Analysis Algorithms
        6. R9.6—Built-In Self-Repair
  18. 10. Boundary Scan and Core-Based Testing
    1. About this Chapter
    2. 10.1. Introduction
      1. 10.1.1. IEEE 1149 Standard Family
      2. 10.1.2. Core-Based Design and Test Considerations
    3. 10.2. Digital Boundary Scan (IEEE Std. 1149.1)
      1. 10.2.1. Basic Concept
      2. 10.2.2. Overall 1149.1 Test Architecture and Operations
      3. 10.2.3. Test Access Port and Bus Protocols
      4. 10.2.4. Data Registers and Boundary-Scan Cells
      5. 10.2.5. TAP Controller
      6. 10.2.6. Instruction Register and Instruction Set
      7. 10.2.7. Boundary-Scan Description Language
      8. 10.2.8. On-Chip Test Support with Boundary Scan
      9. 10.2.9. Board and System-Level Boundary-Scan Control Architectures
    4. 10.3. Boundary Scan for Advanced Networks (IEEE 1149.6)
      1. 10.3.1. Rationale for 1149.6
      2. 10.3.2. 1149.6 Analog Test Receiver
      3. 10.3.3. 1149.6 Digital Driver Logic
      4. 10.3.4. 1149.6 Digital Receiver Logic
      5. 10.3.5. 1149.6 Test Access Port (TAP)
      6. 10.3.6. Summary
    5. 10.4. Embedded Core Test Standard (IEEE Std. 1500)
      1. 10.4.1. SOC (System-on-Chip) Test Problems
      2. 10.4.2. Overall Architecture
      3. 10.4.3. Wrapper Components and Functions
      4. 10.4.4. Instruction Set
      5. 10.4.5. Core Test Language (CTL)
      6. 10.4.6. Core Test Supporting and System Test Configurations
      7. 10.4.7. Hierarchical Test Control and Plug-and-Play
    6. 10.5. Comparisons between the 1500 and 1149.1 Standards
    7. 10.6. Concluding Remarks
    8. 10.7. Exercises
    9. Acknowledgments
    10. References
        1. R10.0—Books
        2. R10.1—Introduction
        3. R10.2—Digital Boundary Scan (IEEE Std. 1149.1)
        4. R10.3—Boundary-Scan Extension (IEEE Std. 1149.6)
        5. R10.4—Embedded Core Test Standard (IEEE Std. 1500)
        6. R10.6—Concluding Remarks
  19. 11. Analog and Mixed-Signal Testing
    1. About this Chapter
    2. 11.1. Introduction
      1. 11.1.1. Analog Circuit Properties
        1. 11.1.1.1. Continuous Signals
        2. 11.1.1.2. Large Range of Circuits
        3. 11.1.1.3. Nonlinear Characteristics
        4. 11.1.1.4. Feedback Ambiguity
        5. 11.1.1.5. Complicated Cause–Effect Relationship
        6. 11.1.1.6. Absence of Suitable Fault Model
        7. 11.1.1.7. Requirement for Accurate Instruments for Measuring Analog Signals
      2. 11.1.2. Analog Defect Mechanisms and Fault Models
        1. 11.1.2.1. Hard Faults
        2. 11.1.2.2. Soft Faults
    3. 11.2. Analog Circuit Testing
      1. 11.2.1. Analog Test Approaches
      2. 11.2.2. Analog Test Waveforms
      3. 11.2.3. DC Parametric Testing
        1. 11.2.3.1. Open-Loop Gain Measurement
        2. 11.2.3.2. Unit Gain Bandwidth Measurement
        3. 11.2.3.3. Common Mode Rejection Ratio Measurement
        4. 11.2.3.4. Power Supply Rejection Ratio Measurement
      4. 11.2.4. AC Parametric Testing
        1. 11.2.4.1. Maximal Output Amplitude Measurement
        2. 11.2.4.2. Frequency Response Measurement
        3. 11.2.4.3. SNR and Distortion Measurement
        4. 11.2.4.4. Intermodulation Distortion Measurement
    4. 11.3. Mixed-Signal Testing
      1. 11.3.1. Introduction to Analog–Digital Conversion
      2. 11.3.2. ADC and DAC Circuit Structure
        1. 11.3.2.1. DAC Circuit Structure
        2. 11.3.2.2. ADC Circuit Structure
      3. 11.3.3. ADC/DAC Specification and Fault Models
      4. 11.3.4. IEEE 1057 Standard
      5. 11.3.5. Time-Domain ADC Testing
        1. 11.3.5.1. Code Bins
        2. 11.3.5.2. Code Transition Level Test (Static)
        3. 11.3.5.3. Code Transition Level Test (Dynamic)
        4. 11.3.5.4. Gain and Offset Test
        5. 11.3.5.5. Linearity Error and Maximal Static Error
        6. 11.3.5.6. Sine Wave Curve-Fit Test
      6. 11.3.6. Frequency-Domain ADC Testing
    5. 11.4. IEEE 1149.4 Standard for a Mixed-Signal Test Bus
      1. 11.4.1. IEEE 1149.4 Overview
        1. 11.4.1.1. Scope of the Standard
      2. 11.4.2. IEEE 1149.4 Circuit Structures
      3. 11.4.3. IEEE 1149.4 Instructions
        1. 11.4.3.1. Mandatory Instructions
        2. 11.4.3.2. Optional Instructions
      4. 11.4.4. IEEE 1149.4 Test Modes
        1. 11.4.4.1. Open/Short Interconnect Testing
        2. 11.4.4.2. Extended Interconnect Measurement
        3. 11.4.4.3. Complex Network Measurement
        4. 11.4.4.4. High-Performance Configuration
    6. 11.5. Concluding Remarks
    7. 11.6. Exercises
    8. Acknowledgments
    9. References
        1. R11.0—Books
        2. R11.1—Introduction
        3. R11.2—Analog Circuit Testing
  20. 12. Test Technology Trends in the Nanometer Age
    1. About this Chapter
    2. 12.1. Test Technology Roadmap
    3. 12.2. Delay Testing
      1. 12.2.1. Test Application Schemes for Testing Delay Defects
      2. 12.2.2. Delay Fault Models
      3. 12.2.3. Summary
    4. 12.3. Coping with Physical Failures, Soft Errors, and Reliability Issues
      1. 12.3.1. Signal Integrity and Power Supply Noise
        1. 12.3.1.1. Integrity Loss Fault Model
        2. 12.3.1.2. Location
        3. 12.3.1.3. Pattern Generation
        4. 12.3.1.4. Sensing and Readout
      2. 12.3.2. Parametric Defects, Process Variations, and Yield
        1. 12.3.2.1. Defect-Based Test
      3. 12.3.3. Soft Errors
      4. 12.3.4. Fault Tolerance
      5. 12.3.5. Defect and Error Tolerance
    5. 12.4. FPGA Testing
      1. 12.4.1. Impact of Programmability
      2. 12.4.2. Testing Approaches
      3. 12.4.3. Built-In Self-Test of Logic Resources
      4. 12.4.4. Built-In Self-Test of Routing Resources
      5. 12.4.5. Recent Trends
    6. 12.5. MEMS Testing
      1. 12.5.1. Basic Concepts for Capacitive MEMS Devices
      2. 12.5.2. MEMS Built-In Self-Test
        1. 12.5.2.1. Sensitivity BIST Scheme
        2. 12.5.2.2. Symmetry BIST Scheme
        3. 12.5.2.3. A Dual-Mode BIST Technique
      3. 12.5.3. A BIST Example for MEMS Comb Accelerometers
      4. 12.5.4. Conclusions
    7. 12.6. High-speed I/O Testing
      1. 12.6.1. I/O Interface Technology and Trend
      2. 12.6.2. I/O Testing and Challenges
      3. 12.6.3. High-Performance I/O Test Solutions
      4. 12.6.4. Future Challenges
    8. 12.7. RF Testing
      1. 12.7.1. Core RF Building Blocks
      2. 12.7.2. RF Test Specifications and Measurement Procedures
        1. 12.7.2.1. Gain
        2. 12.7.2.2. Conversion Gain
        3. 12.7.2.3. Third-Order Intercept
        4. 12.7.2.4. Noise Figure
      3. 12.7.3. Tests for System-Level Specifications
        1. 12.7.3.1. Adjacent Channel Power Ratio
        2. 12.7.3.2. Error Vector Magnitude, Magnitude Error, and Phase Error
      4. 12.7.4. Current and Future Trends
        1. 12.7.4.1. Future Trends
    9. 12.8. Concluding Remarks
    10. Acknowledgments
    11. References
        1. R12.0—Books
        2. R12.1—Test Technology Roadmap
        3. R12.2—Delay Testing
        4. R12.3—Coping with Physical Failures, Soft Errors, and Reliability Issues
        5. R12.4—FPGA Testing
        6. R12.5—MEMS Testing
        7. R12.6—High-Speed I/O Testing
        8. R12.7—RF Testing
        9. R12.8—Concluding Remarks

Product information

  • Title: VLSI Test Principles and Architectures
  • Author(s): Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Khader S. Abdel-Hafez, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C.-M. Li, Mike Peng Li, Xiaowei Li, T.M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Soumendu Bhattacharya, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Erik H. Volkerink, Duncan Walker, Shianling Wu, Nur A. Touba, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting Cheng, William Eklow, Michael S. Hsiao, Jiun-Lang Huang, Shi-Yu Huang
  • Release date: August 2006
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080474793