VLSI Digital Signal Processing Systems: Design and Implementation

3.5    CONCLUSIONS

This chapter has addressed the methodologies of pipelining and parallel processing in the context of nonrecursive digital filters. Both approaches can be used to increase the sampling frequency of a filter. In pipelining, pipelining latches are placed across the feed-forward cutsets in the SFG and the computation time of the critical path is reduced. As a result, the clock frequency can be increased and hence the sampling rate is increased. In parallel processing, the hardware for the original serial system is duplicated and the resulting system is an MIMO parallel system. In this case, the clock frequency stays the same, and the sampling frequency is increased. Use of pipelining and parallel processing for low-power design has been illustrated. The basic idea is to trade the increased sampling speed for reduction of power consumption using lower supply voltage. Parallel FIR filters can be implemented using less than linear increase in hardware with respect to the level of parallelism using fast algorithms (see Chapter 9). Pipelining and parallel processing of recursive digital filters using look-ahead techniques are addressed in Chapter 10.