VLSI Design Methodology Development, First Edition

Chapter 19. Design for Testability Analysis

19.1 Stuck-at Fault Models and Automated Test Pattern Generation (ATPG)

This chapter briefly reviews some of the techniques developed to assist SoC designers prepare an efficient, yet thorough, set of production test patterns. The cost of tester time is a significant contribution to overall product cost and is thus a major consideration when the SoC design and methodology teams are defining the design for testability (DFT) architecture to be incorporated. The tester cost is weighed against the subsequent impact of discovering failures at final product testing or, worse, end customer failures. This DFT assessment helps establish production test coverage targets (and related test escape estimates). ...