VLSI Architectures for Modern Error-Correcting Codes

List of Figures

1.1   Standard basis multiplier architecture (Modified from [7])

1.2   Normal basis multiplier architecture

1.3   Implementation architecture of inversion over GF(2^q) (Scheme A)

1.4   Implementation architecture of inversion over GF(2^q) (Scheme A, iterative approach)

1.5   Implementation architecture of inversion over GF(2⁸) (Scheme B)

1.6   Implementation architecture of inversion over GF(2⁸) (Scheme C)

2.1   Circuits with feedback loops

2.2   Example of DFG. (a) block diagram of a filter; (b) corresponding DFG

2.3   Cutset examples

2.4   Pipelining example, (a) an FIR filter; (b)(c) pipelined filters

2.5   A retimed version of the filter

2.6   An example of filter retiming for achieving iteration bound.

2.7   Example of applying ...