VHDL: Programming by Example

CHAPTER 8

Advanced Topics

In this chapter, some of the more esoteric features of VHDL are discussed. Some of the features may be useful for certain types of designs, and not for others. Typical usage examples are presented to show how these features might be taken advantage of.

Some of the features discussed include overloading, qualified expressions, user-defined attributes, generate statements, aliases, and TextIO. All of these features provide the user with an advanced environment with which to do modeling.

Overloading

Overloading allows the designer to write much more readable code. An object is overloaded when the same object name exists ...