VHDL: Programming by Example

VHDL: Programming by Example

by Douglas Perry
Released May 2002
Publisher(s): McGraw-Hill
ISBN: 9780071400701

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Book description

This is the hands-down favorite users guide to VHDL. It is completely updated to reflect the very latest design methods CD-ROM with working code examples, verification tools and more. No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast-or as painlessly-as this classic tutorial from master teacher Doug Perry.

Table of contents

  1. Cover
  2. VHDL: Programming by Example, Fourth Edition
  3. Copyright Page
  4. CD Content
  5. Dedication
  6. CONTENTS
  7. Foreword
  8. Preface
  9. Acknowledgments
  10. Chapter 1 Introduction to VHDL
    1. VHDL Terms
    2. Describing Hardware in VHDL
    3. Entity
      1. Architectures
      2. Concurrent Signal Assignment
      3. Event Scheduling
      4. Statement Concurrency
      5. Structural Designs
      6. Sequential Behavior
      7. Process Statements
      8. Process Declarative Region
      9. Process Statement Part
      10. Process Execution
      11. Sequential Statements
      12. Architecture Selection
      13. Configuration Statements
      14. Power of Configurations
  11. Chapter 2 Behavioral Modeling
    1. Introduction to Behavioral Modeling
    2. Transport Versus Inertial Delay
      1. Inertial Delay
      2. Transport Delay
      3. Inertial Delay Model
      4. Transport Delay Model
    3. Simulation Deltas
    4. Drivers
      1. Driver Creation
      2. Bad Multiple Driver Model
    5. Generics
    6. Block Statements
      1. Guarded Blocks
  12. Chapter 3 Sequential Processing
    1. Process Statement
      1. Sensitivity List
      2. Process Example
    2. Signal Assignment Versus Variable Assignment
      1. Incorrect Mux Example
      2. Correct Mux Example
    3. Sequential Statements
    4. IF Statements
    5. CASE Statements
    6. LOOP Statements
      1. NEXT Statement
    7. EXIT Statement
    8. ASSERT Statement
      1. Assertion BNF
    9. WAIT Statements
      1. WAIT ON Signal
      2. WAIT UNTIL Expression
      3. WAIT FOR time_expression
      4. Multiple WAIT Conditions
      5. WAIT Time-Out
      6. Sensitivity List Versus WAIT Statement
    10. Concurrent Assignment Problem
    11. Passive Processes
  13. Chapter 4 Data Types
    1. Object Types
      1. Signal
      2. Variables
      3. Constants
    2. Data Types
      1. Scalar Types
      2. Composite Types
      3. Incomplete Types
      4. File Types
    3. File Type Caveats
    4. Subtypes
  14. Chapter 5 Subprograms and Packages
    1. Subprograms
      1. Function
      2. Conversion Functions
      3. Resolution Functions
      4. Procedures
    2. Packages
      1. Package Declaration
      2. Deferred Constants
      3. Subprogram Declaration
      4. Package Body
  15. Chapter 6 Predefined Attributes
    1. Value Kind Attributes
      1. Value Type Attributes
      2. Value Array Attributes
      3. Value Block Attributes
    2. Function Kind Attributes
      1. Function Type Attributes
      2. Function Array Attributes
      3. Function Signal Attributes
      4. Attributes ’EVENT and ’LAST_VALUE
      5. Attribute ’LAST_EVENT
      6. Attribute ’ACTIVE and ’LAST_ACTIVE
    3. Signal Kind Attributes
      1. Attribute ’DELAYED
      2. Attribute ’STABLE
      3. Attribute ’QUIET
      4. Attribute ’TRANSACTION
    4. Type Kind Attributes
    5. Range Kind Attributes
  16. Chapter 7 Configurations
    1. Default Configurations
    2. Component Configurations
      1. Lower-Level Configurations
      2. Entity-Architecture Pair Configuration
      3. Port Maps
    3. Mapping Library Entities
    4. Generics in Configurations
    5. Generic Value Specification in Architecture
    6. Generic Specifications in Configurations
    7. Board-Socket-Chip Analogy
    8. Block Configurations
    9. Architecture Configurations
  17. Chapter 8 Advanced Topics
    1. Overloading
      1. Subprogram Overloading
      2. Overloading Operators
    2. Aliases
    3. Qualified Expressions
    4. User-Defined Attributes
    5. Generate Statements
      1. Irregular Generate Statement
    6. TextIO
  18. Chapter 9 Synthesis
    1. Register Transfer Level Description
    2. Constraints
      1. Timing Constraints
      2. Clock Constraints
    3. Attributes
      1. Load
      2. Drive
      3. Arrival Time
    4. Technology Libraries
    5. Synthesis
      1. Translation
      2. Boolean Optimization
      3. Flattening
      4. Factoring
      5. Mapping to Gates
  19. Chapter 10 VHDL Synthesis
    1. Simple Gate — Concurrent Assignment
    2. IF Control Flow Statements
    3. Case Control Flow Statements
    4. Simple Sequential Statements
    5. Asynchronous Reset
    6. Asynchronous Preset and Clear
    7. More Complex Sequential Statements
      1. Four-Bit Shifter
    8. State Machine Example
  20. Chapter 11 High Level Design Flow
    1. RTL Simulation
    2. VHDL Synthesis
    3. Functional Gate-Level Verification
    4. Place and Route
    5. Post Layout Timing Simulation
    6. Static Timing
  21. Chapter 12 Top-Level System Design
    1. CPU Design
    2. Top-Level System Operation
    3. Instructions
    4. Sample Instruction Representation
    5. CPU Top-Level Design
      1. Block Copy Operation
  22. Chapter 13 CPU: Synthesis Description
    1. ALU
    2. Comp
    3. Control
    4. Reg
    5. Regarray
    6. Shift
    7. Trireg
  23. Chapter 14 CPU: RTL Simulation
    1. Testbenches
      1. Kinds of Testbenches
      2. Stimulus Only
      3. Full Testbench
      4. Simulator Specific
      5. Hybrid Testbenches
      6. Fast Testbench
    2. CPU Simulation
  24. Chapter 15 CPU Design: Synthesis Results
  25. Chapter 16 Place and Route
    1. Place and Route Process
    2. Placing and Routing the Device
      1. Setting up a project
  26. Chapter 17 CPU: VITAL Simulation
    1. VITAL Library
    2. VITAL Simulation Process Overview
    3. VITAL Implementation
    4. Simple VITAL Model
    5. VITAL Architecture
      1. Wire Delay Section
      2. Flip-Flop Example
    6. SDF File
      1. VITAL Simulation
    7. Back-Annotated Simulation
  27. Chapter 18 At Speed Debugging Techniques
    1. Instrumentor
    2. Debugger
    3. Debug CPU Design
      1. Create Project
      2. Specify Top-Level Parameters
      3. Specify Project Parameters
    4. Instrument Signals
    5. Write Instrumented Design
    6. Implement New Design
    7. Start Debug
    8. Enable Breakpoint
    9. Trigger Position
    10. Waveform Display
    11. Set Watchpoint
    12. Complex Triggers
  28. Appendix A Standard Logic Package
  29. Appendix B VHDL Reference Tables
  30. Appendix C Reading VHDL BNF
  31. Appendix D VHDL93 Updates
    1. Alias
    2. Attribute Changes
    3. Bit String Literal
    4. DELAY_LENGTH Subtype
    5. Direct Instantiation
    6. Extended Identifiers
    7. File Operations
    8. Foreign Interface
    9. Generate Statement Changes
    10. Globally Static Assignment
    11. Groups
    12. Incremental Binding
    13. Postponed Process
    14. Pure and Impure Functions
    15. Pulse Reject
    16. Report Statement
    17. Shared Variables
    18. Shift Operators
      1. SLL — shift left logical
      2. SRL — shift right logical
      3. SLA — shift left arithmetic
      4. SRA — shift right arithmetic
      5. ROL — rotate left
      6. ROR — rotate right
    19. Syntax Consistency
    20. Unaffected
    21. XNOR Operator
  32. Index
  33. About the Author
  34. For Download

Product information

  • Title: VHDL: Programming by Example
  • Author(s): Douglas Perry
  • Release date: May 2002
  • Publisher(s): McGraw-Hill
  • ISBN: 9780071400701