Vhdl for Logic Synthesis, Third Edition

Vhdl for Logic Synthesis, Third Edition

by Andrew Rushton
Released May 2011
Publisher(s): Wiley
ISBN: 9780470688472

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Book description

Making VHDL a simple and easy-to-use hardware description language

Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.

This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.

Features to this edition include:

  • a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies

  • a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting

  • a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches

  • a chapter on writing test benches, with everything needed to implement a test-based design strategy

  • extensive coverage of data path design, including integer, fixed-point and floating-point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders

Focused specifically on logic synthesis, this book is for professional hardware engineers using VHDL for logic synthesis, and digital systems designers new to VHDL but familiar with digital systems. It offers all the knowledge and tools needed to use VHDL for logic synthesis. Organised in themed chapters and with a comprehensive index, this complete reference will also benefit postgraduate students following courses on microelectronics or VLSI/ semiconductors and digital design.

Table of contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Preface
  5. List of Figures
  6. List of Tables
  7. Chapter 1: Introduction
    1. 1.1 The VHDL Design Cycle
    2. 1.2 The Origins of VHDL
    3. 1.3 The Standardisation Process
    4. 1.4 Unification of VHDL Standards
    5. 1.5 Portability
  8. Chapter 2: Register-Transfer Level Design
    1. 2.1 The RTL Design Stages
    2. 2.2 Example Circuit
    3. 2.3 Identify the Data Operations
    4. 2.4 Determine the Data Precision
    5. 2.5 Choose Resources to Provide
    6. 2.6 Allocate Operations to Resources
    7. 2.7 Design the Controller
    8. 2.8 Design the Reset Mechanism
    9. 2.9 VHDL Description of the RTL Design
    10. 2.10 Synthesis Results
  9. Chapter 3: Combinational Logic
    1. 3.1 Design Units
    2. 3.2 Entities and Architectures
    3. 3.3 Simulation Model
    4. 3.4 Synthesis Templates
    5. 3.5 Signals and Ports
    6. 3.6 Initial Values
    7. 3.7 Simple Signal Assignments
    8. 3.8 Conditional Signal Assignments
    9. 3.9 Selected Signal Assignment
    10. 3.10 Worked Example
  10. Chapter 4: Basic Types
    1. 4.1 Synthesisable Types
    2. 4.2 Standard Types
    3. 4.3 Standard Operators
    4. 4.4 Type Bit
    5. 4.5 Type Boolean
    6. 4.6 Integer Types
    7. 4.7 Enumeration Types
    8. 4.8 Multi-Valued Logic Types
    9. 4.9 Records
    10. 4.10 Arrays
    11. 4.11 Aggregates, Strings and Bit-Strings
    12. 4.12 Attributes
    13. 4.13 More on Selected Signal Assignments
  11. Chapter 5: Operators
    1. 5.1 The Standard Operators
    2. 5.2 Operator Precedence
    3. 5.3 Boolean Operators
    4. 5.4 Comparison Operators
    5. 5.5 Shifting Operators
    6. 5.6 Arithmetic Operators
    7. 5.7 Concatenation Operator
  12. Chapter 6: Synthesis Types
    1. 6.1 Synthesis Type System
    2. 6.2 Making the Packages Visible
    3. 6.3 Logic Types – Std_Logic_1164
    4. 6.4 Numeric Types – Numeric_Std
    5. 6.5 Fixed-Point Types – Fixed_Pkg
    6. 6.6 Floating-Point Types – Float_Pkg
    7. 6.7 Type Conversions
    8. 6.8 Constant Values
    9. 6.9 Mixing Types in Expressions
    10. 6.10 Top-Level Interface
  13. Chapter 7: Std_Logic_Arith
    1. 7.1 The Std_Logic_Arith Package
    2. 7.2 Contents of Std_Logic_Arith
    3. 7.3 Type Conversions
    4. 7.4 Constant Values
    5. 7.5 Mixing Types in Expressions
  14. Chapter 8: Sequential VHDL
    1. 8.1 Processes
    2. 8.2 Signal Assignments
    3. 8.3 Variables
    4. 8.4 If Statements
    5. 8.5 Case Statements
    6. 8.6 Latch Inference
    7. 8.7 Loops
    8. 8.8 Worked Example
  15. Chapter 9: Registers
    1. 9.1 Basic D-Type Register
    2. 9.2 Simulation Model
    3. 9.3 Synthesis Model
    4. 9.4 Register Templates
    5. 9.5 Register Types
    6. 9.6 Clock Types
    7. 9.7 Clock Gating
    8. 9.8 Data Gating
    9. 9.9 Asynchronous Reset
    10. 9.10 Synchronous Reset
    11. 9.11 Registered Variables
    12. 9.12 Initial Values
  16. Chapter 10: Hierarchy
    1. 10.1 The Role of Components
    2. 10.2 Indirect Binding
    3. 10.3 Direct Binding
    4. 10.4 Component Packages
    5. 10.5 Parameterised Components
    6. 10.6 Generate Statements
    7. 10.7 Worked Examples
  17. Chapter 11: Subprograms
    1. 11.1 The Role of Subprograms
    2. 11.2 Functions
    3. 11.3 Operators
    4. 11.4 Type Conversions
    5. 11.5 Procedures
    6. 11.6 Declaring Subprograms
    7. 11.7 Worked Example
  18. Chapter 12: Special Structures
    1. 12.1 Tristates
    2. 12.2 Finite State Machines
    3. 12.3 RAMs and Register Banks
    4. 12.4 Decoders and ROMs
  19. Chapter 13: Test Benches
    1. 13.1 Test Benches
    2. 13.2 Combinational Test Bench
    3. 13.3 Verifying Responses
    4. 13.4 Clocks and Resets
    5. 13.5 Other Standard Types
    6. 13.6 Don't Care Outputs
    7. 13.7 Printing Response Values
    8. 13.8 Using TextIO to Read Data Files
    9. 13.9 Reading Standard Types
    10. 13.10 TextIO Error Handling
    11. 13.11 TextIO for Synthesis Types
    12. 13.12 TextIO for User-Defined Types
    13. 13.13 Worked Example
  20. Chapter 14: Libraries
    1. 14.1 The Library
    2. 14.2 Library Names
    3. 14.3 Library Work
    4. 14.4 Standard Libraries
    5. 14.5 Organising Your Files
    6. 14.6 Incremental Compilation
  21. Chapter 15: Case Study
    1. 15.1 Specification
    2. 15.2 System-Level Design
    3. 15.3 RTL Design
    4. 15.4 Trial Synthesis
    5. 15.5 Testing the Design
    6. 15.6 Floating-Point Version
    7. 15.7 Final Synthesis
    8. 15.8 Generic Version
    9. 15.9 Conclusions
  22. Appendix A: Package Listings
    1. A.1 Package Standard
    2. A.2 Package Standard_Additions
    3. A.3 Package Std_Logic_1164
    4. A.4 Package Std_Logic_1164_Additions
    5. A.5 Package Numeric_Std
    6. A.6 Package Numeric_Std_Additions
    7. A.7 Package Fixed_Float_Types
    8. A.8 Package Fixed_Pkg
    9. A.9 Package Float_Pkg
    10. A.10 Package TextIO
    11. A.11 Package Standard_Textio_Additions
    12. A.12 Package Std_Logic_Arith
    13. A.13 Package Math_Real
  23. Appendix B: Syntax Reference
    1. B.1 Keywords
    2. B.2 Design Units
    3. B.3 Concurrent Statements
    4. B.4 Sequential Statements
    5. B.5 Expressions
    6. B.6 Declarations
  24. References
  25. Index

Product information

  • Title: Vhdl for Logic Synthesis, Third Edition
  • Author(s): Andrew Rushton
  • Release date: May 2011
  • Publisher(s): Wiley
  • ISBN: 9780470688472