Verilog HDL Design Examples

Verilog HDL Design Examples

by Joseph Cavanagh
Released October 2017
Publisher(s): CRC Press
ISBN: 9781351596299

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Book description

The book presents the Verilog language with a variety of examples to provide a firm foundation in the design of the digital system using Verilog HDL. It places emphasis on the detailed design of various Verilog projects that include the design module, test bench module, and outputs from the simulator illustrating the design's functional operation.

Table of contents

  1. Cover
  2. Halftitle Page
  3. Title Page
  4. Copyright
  5. Table of Contents
    1. Preface
    2. Chapter 1 Introduction to Logic Design Using Verilog HDL
      1. 1.1 Logic Elements
        1. 1.1.1 Comments
        2. 1.1.2 Logic Gates
        3. 1.1.3 Logic Macro Functions
        4. 1.1.4 Procedural Flow Control
        5. 1.1.5 Net Data Types
        6. 1.1.6 Register Data Types
      2. 1.2 Expressions
        1. 1.2.1 Operands
        2. 1.2.2 Operators
      3. 1.3 Modules and Ports
        1. 1.3.1 Designing a Test Bench for Simulation
      4. 1.4 Built-In Primitives
        1. 1.4.1 Built-In Primitive Design Examples
      5. 1.5 User-Defined Primitives
        1. 1.5.1 Defining a User-Defined Primitive
        2. 1.5.2 Combinational User-Defined Primitives
        3. 1.5.3 Sequential User-Defined Primitives
      6. 1.6 Dataflow Modeling
        1. 1.6.1 Continuous Assignment
        2. 1.6.2 Reduction Operators
        3. 1.6.3 Conditional Operator
        4. 1.6.4 Relational Operators
        5. 1.6.5 Logical Operators
        6. 1.6.6 Bitwise Operators
        7. 1.6.7 Shift Operators
      7. 1.7 Behavioral Modeling
        1. 1.7.1 Initial Statement
        2. 1.7.2 Always Statement
        3. 1.7.3 Intrastatement Delay
        4. 1.7.4 Interstatement Delay
        5. 1.7.5 Blocking Assignments
        6. 1.7.6 Nonblocking Assignments
        7. 1.7.7 Conditional Statements
        8. 1.7.8 Case Statement
        9. 1.7.9 Loop Statements
        10. 1.7.10 Logical, Algebraic, and Rotate Shift Operations
      8. 1.8 Structural Modeling
        1. 1.8.1 Module Instantiation
        2. 1.8.2 Ports
        3. 1.8.3 Design Examples
      9. 1.9 Tasks and Functions
        1. 1.9.1 Task Declaration
        2. 1.9.2 Task Invocation
        3. 1.9.3 Function Declaration
        4. 1.9.4 Function Invocation
      10. 1.10 Problems
    3. Chapter 2 Combinational Logic Design Using Verilog HDL
      1. 2.1 Number Systems
        1. 2.1.1 Binary Number System
        2. 2.1.2 Octal Number System
        3. 2.1.3 Decimal Number System
        4. 2.1.4 Hexadecimal Number System
      2. 2.2 Boolean Algebra
        1. 2.2.1 Axioms
        2. 2.2.2 Theorems
        3. 2.2.3 Other Terms for Boolean Algebra
      3. 2.3 Logic Equations
      4. 2.4 Multiplexers
      5. 2.5 Comparators
      6. 2.6 Programmable Logic Devices
        1. 2.6.1 Programmable Read-Only Memories
        2. 2.6.2 Programmable Array Logic
        3. 2.6.3 Programmable Logic Array
      7. 2.7 Additional Design Examples
      8. 2.8 Problems
    4. Chapter 3 Sequential Logic Design Using Verilog HDL
      1. 3.1 Introduction
        1. 3.1.1 Definition of a Sequential Machine
      2. 3.2 Synchronous Sequential Machines
        1. 3.2.1 Synthesis Procedure
        2. 3.2.2 Equivalent States
        3. 3.2.4 Mealy Machines
        4. 3.2.5 Synchronous Registers
        5. 3.2.6 Synchronous Counters
      3. 3.3 Asynchronous Sequential Machines
        1. 3.3.1 Synthesis Procedure
        2. 3.3.2 Hazards
        3. 3.3.3 Oscillations
        4. 3.3.4 Races
        5. 3.3.5 Design Examples of Asynchronous Sequential Machines
      4. 3.4 Pulse-Mode Asynchronous Sequential Machines
        1. 3.4.1 Synthesis Procedure
        2. 3.4.2 SR Latches with D Flip-Flops as Storage Elements
        3. 3.4.3 T Flip-Flops as Storage Elements
      5. 3.5 Problems
    5. Chapter 4 Computer Arithmetic Design Using Verilog HDL
      1. 4.1 Introduction
      2. 4.2 Fixed-Point Addition
        1. 4.2.1 Full Adder
        2. 4.2.2 Three-Bit Adder
        3. 4.2.3 Four-Bit Ripple-Carry Adder
        4. 4.2.4 Carry Lookahead Adder
      3. 4.3 Fixed-Point Subtraction
        1. 4.3.1 Four-Bit Ripple Subtractor
        2. 4.3.2 Eight-Bit Subtractor
        3. 4.3.3 Four-Bit Dataflow Adder/Subtractor
        4. 4.3.4 Eight-Bit Behavioral Adder/Subtractor
      4. 4.4 Fixed-Point Multiplication
        1. 4.4.1 Behavioral Four-Bit Multiplier
        2. 4.4.2 Three-Bit Array Multiplier
        3. 4.4.3 Four-Bit Dataflow Multiplication Using the Multiply Operator
      5. 4.5 Fixed-Point Division
    6. 4.6 Arithmetic and Logic Unit
    7. 4.7 Decimal Addition
      1. 4.7.1 Decimal Addition with Sum Correction
      2. 4.7.2 Decimal Addition Using Multiplexers for Sum Correction
    8. 4.8 Decimal Subtraction
      1. 4.8.1 Decimal Subtraction Using Full Adders and Built-In Primitives for Four Bits
      2. 4.8.2 Decimal/Binary Subtraction Using Full Adders and Built-In Primitives for Eight Bits
      3. 4.8.3 Eight-Bit Decimal Subtraction Unit with Built-In Primitives and Full Adders Designed Using Behavioral Modeling
    9. 4.9 Decimal Multiplication
    10. 4.10 Decimal Division
    11. 4.11 Floating-Point Addition
    12. 4.12 Floating-Point Subtraction
      1. 4.12.1 True Addition and True Subtraction
      2. 4.13 Floating-Point Multiplication
      3. 4.14 Floating-Point Division
      4. 4.15 Problems
    13. Appendix A Event Queue
    14. Appendix B Verilog Project Procedure
    15. Appendix C Answers to Select Problems
    16. Index

Product information

  • Title: Verilog HDL Design Examples
  • Author(s): Joseph Cavanagh
  • Release date: October 2017
  • Publisher(s): CRC Press
  • ISBN: 9781351596299