Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

Appendix C. List of Keywords, System Tasks, and Compiler Directives

Keywords

Keywords^[1] are predefined, nonescaped identifiers that define the language constructs. An escaped identifier is never treated as a keyword. All keywords are defined in lowercase.

The list is sorted in alphabetical order.

always	ifnone	rnmos
and	incdir	rpmos
assign	include	rtran
automatic	initial	rtranif0
begin	inout	rtranif1
buf	input	scalared
bufif0	instance	showcancelled
bufif1	integer	signed
case	join	small
casex	large	specify
casez	liblist	specparam
cell	library	strong0
cmos	localparam	strong1
config	macromodule	supply0
deassign	medium	supply1
default	module	table
defparam	nand	task
design	negedge	time
disable	nmos	tran
edge	nor	tranif0
else	noshowcancelled	tranif1
end	not	tri
endcase	notif0	tri0
endconfig	notif1	tri1
endfunction	or	triand ...