Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

by Samir Palnitkar
Released February 2003
Publisher(s): Pearson
ISBN: 9780130449115

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Book description

VERILOG HDL, Second Editionby Samir PalnitkarWith a Foreword by Prabhu Goel

Written forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.

Among its many features, this edition—

  • Describes state-of-the-art verification methodologies

  • Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling

  • Introduces you to the Programming Language Interface (PLI)

  • Describes logic synthesis methodologies

  • Explains timing and delay simulation

  • Discusses user-defined primitives

  • Offers many practical modeling tips

    • Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.

    About the CD-ROM

    The CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book.

    Whatpeople are saying about Verilog HDL—

    “Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today’smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design."

    —RajeevMadhavan, Chairman and CEO, Magma Design Automation

    “Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques.”

    —MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization

    Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts.”

    —BerendOzceri, Design Engineer, Cisco Systems, Inc.

    “Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook.”

    —Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames

    PRENTICE HALL

    Professional Technical Reference

    Upper Saddle River, NJ 07458

    www.phptr.com

    ISBN: 0-13-044911-3

    Table of contents

    1. Copyright
      1. Dedication
    2. About the Author
    3. List of Figures
    4. List of Tables
    5. List of Examples
    6. Foreword
    7. Preface
      1. Who Should Use This Book
      2. How This Book Is Organized
      3. Conventions Used in This Book
    8. Acknowledgments
    9. 1. Basic Verilog Topics
      1. 1. Overview of Digital Design with Verilog HDL
        1. 1.1. Evolution of Computer-Aided Digital Design
        2. 1.2. Emergence of HDLs
        3. 1.3. Typical Design Flow
        4. 1.4. Importance of HDLs
        5. 1.5. Popularity of Verilog HDL
        6. 1.6. Trends in HDLs
      2. 2. Hierarchical Modeling Concepts
        1. 2.1. Design Methodologies
        2. 2.2. 4-bit Ripple Carry Counter
        3. 2.3. Modules
        4. 2.4. Instances
        5. 2.5. Components of a Simulation
        6. 2.6. Example
          1. 2.6.1. Design Block
          2. 2.6.2. Stimulus Block
        7. 2.7. Summary
        8. 2.8. Exercises
      3. 3. Basic Concepts
        1. 3.1. Lexical Conventions
          1. 3.1.1. Whitespace
          2. 3.1.2. Comments
          3. 3.1.3. Operators
          4. 3.1.4. Number Specification
            1. Sized numbers
            2. Unsized numbers
            3. X or Z values
            4. Negative numbers
            5. Underscore characters and question marks
          5. 3.1.5. Strings
          6. 3.1.6. Identifiers and Keywords
          7. 3.1.7. Escaped Identifiers
        2. 3.2. Data Types
          1. 3.2.1. Value Set
          2. 3.2.2. Nets
          3. 3.2.3. Registers
          4. 3.2.4. Vectors
            1. Vector Part Select
            2. Variable Vector Part Select
          5. 3.2.5. Integer , Real, and Time Register Data Types
            1. Integer
            2. Real
            3. Time
          6. 3.2.6. Arrays
          7. 3.2.7. Memories
          8. 3.2.8. Parameters
          9. 3.2.9. Strings
        3. 3.3. System Tasks and Compiler Directives
          1. 3.3.1. System Tasks
            1. Displaying information
            2. Monitoring information
            3. Stopping and finishing in a simulation
          2. 3.3.2. Compiler Directives
            1. `define
            2. `include
        4. 3.4. Summary
        5. 3.5. Exercises
      4. 4. Modules and Ports
        1. 4.1. Modules
        2. 4.2. Ports
          1. 4.2.1. List of Ports
          2. 4.2.2. Port Declaration
          3. 4.2.3. Port Connection Rules
            1. Inputs
            2. Outputs
            3. Inouts
            4. Width matching
            5. Unconnected ports
            6. Example of illegal port connection
          4. 4.2.4. Connecting Ports to External Signals
            1. Connecting by ordered list
            2. Connecting ports by name
        3. 4.3. Hierarchical Names
        4. 4.4. Summary
        5. 4.5. Exercises
      5. 5. Gate-Level Modeling
        1. 5.1. Gate Types
          1. 5.1.1. And/Or Gates
          2. 5.1.2. Buf/Not Gates
            1. Bufif/notif
          3. 5.1.3. Array of Instances
          4. 5.1.4. Examples
            1. Gate-level multiplexer
            2. 4-bit Ripple Carry Full Adder
        2. 5.2. Gate Delays
          1. 5.2.1. Rise, Fall, and Turn-off Delays
            1. Rise delay
            2. Fall delay
            3. Turn-off delay
          2. 5.2.2. Min/Typ/Max Values
            1. Min value
            2. Typ val
            3. Max value
          3. 5.2.3. Delay Example
        3. 5.3. Summary
        4. 5.4. Exercises
      6. 6. Dataflow Modeling
        1. 6.1. Continuous Assignments
          1. 6.1.1. Implicit Continuous Assignment
          2. 6.1.2. Implicit Net Declaration
        2. 6.2. Delays
          1. 6.2.1. Regular Assignment Delay
          2. 6.2.2. Implicit Continuous Assignment Delay
          3. 6.2.3. Net Declaration Delay
        3. 6.3. Expressions, Operators, and Operands
          1. 6.3.1. Expressions
          2. 6.3.2. Operands
          3. 6.3.3. Operators
        4. 6.4. Operator Types
          1. 6.4.1. Arithmetic Operators
            1. Binary operators
            2. Unary operators
          2. 6.4.2. Logical Operators
          3. 6.4.3. Relational Operators
          4. 6.4.4. Equality Operators
          5. 6.4.5. Bitwise Operators
          6. 6.4.6. Reduction Operators
          7. 6.4.7. Shift Operators
          8. 6.4.8. Concatenation Operator
          9. 6.4.9. Replication Operator
          10. 6.4.10. Conditional Operator
          11. 6.4.11. Operator Precedence
        5. 6.5. Examples
          1. 6.5.1. 4-to-1 Multiplexer
            1. Method 1: logic equation
            2. Method 2: conditional operator
          2. 6.5.2. 4-bit Full Adder
            1. Method 1: dataflow operators
            2. Method 2: full adder with carry lookahead
          3. 6.5.3. Ripple Counter
        6. 6.6. Summary
        7. 6.7. Exercises
      7. 7. Behavioral Modeling
        1. 7.1. Structured Procedures
          1. 7.1.1. initial Statement
            1. Combined Variable Declaration and Initialization
            2. Combined Port/Data Declaration and Initialization
            3. Combined ANSI C Style Port Declaration and Initialization
          2. 7.1.2. always Statement
        2. 7.2. Procedural Assignments
          1. 7.2.1. Blocking Assignments
          2. 7.2.2. Nonblocking Assignments
            1. Application of nonblocking assignments
        3. 7.3. Timing Controls
          1. 7.3.1. Delay-Based Timing Control
            1. Regular delay control
            2. Intra-assignment delay control
            3. Zero delay control
          2. 7.3.2. Event-Based Timing Control
            1. Regular event control
            2. Named event control
            3. Event OR Control
          3. 7.3.3. Level-Sensitive Timing Control
        4. 7.4. Conditional Statements
        5. 7.5. Multiway Branching
          1. 7.5.1. case Statement
          2. 7.5.2. casex, casez Keywords
        6. 7.6. Loops
          1. 7.6.1. While Loop
          2. 7.6.2. For Loop
          3. 7.6.3. Repeat Loop
          4. 7.6.4. Forever loop
        7. 7.7. Sequential and Parallel Blocks
          1. 7.7.1. Block Types
            1. Sequential blocks
            2. Parallel blocks
          2. 7.7.2. Special Features of Blocks
            1. Nested blocks
            2. Named blocks
            3. Disabling named blocks
        8. 7.8. Generate Blocks
          1. 7.8.1. Generate Loop
          2. 7.8.2. Generate Conditional
          3. 7.8.3. Generate Case
        9. 7.9. Examples
          1. 7.9.1. 4-to-1 Multiplexer
          2. 7.9.2. 4-bit Counter
          3. 7.9.3. Traffic Signal Controller
            1. Specification
            2. Verilog description
            3. Stimulus
        10. 7.10. Summary
        11. 7.11. Exercises
      8. 8. Tasks and Functions
        1. 8.1. Differences between Tasks and Functions
        2. 8.2. Tasks
          1. 8.2.1. Task Declaration and Invocation
          2. 8.2.2. Task Examples
            1. Use of input and output arguments
            2. Asymmetric Sequence Generator
          3. 8.2.3. Automatic (Re-entrant) Tasks
        3. 8.3. Functions
          1. 8.3.1. Function Declaration and Invocation
          2. 8.3.2. Function Examples
            1. Parity calculation
            2. Left/right shifter
          3. 8.3.3. Automatic (Recursive) Functions
          4. 8.3.4. Constant Functions
          5. 8.3.5. Signed Functions
        4. 8.4. Summary
        5. 8.5. Exercises
      9. 9. Useful Modeling Techniques
        1. 9.1. Procedural Continuous Assignments
          1. 9.1.1. assign and deassign
          2. 9.1.2. force and release
            1. force and release on registers
            2. force and release on nets
        2. 9.2. Overriding Parameters
          1. 9.2.1. defparam Statement
          2. 9.2.2. Module_Instance Parameter Values
        3. 9.3. Conditional Compilation and Execution
          1. 9.3.1. Conditional Compilation
          2. 9.3.2. Conditional Execution
        4. 9.4. Time Scales
        5. 9.5. Useful System Tasks
          1. 9.5.1. File Output
            1. Opening a file
            2. Writing to files
            3. Closing files
          2. 9.5.2. Displaying Hierarchy
          3. 9.5.3. Strobing
          4. 9.5.4. Random Number Generation
          5. 9.5.5. Initializing Memory from File
          6. 9.5.6. Value Change Dump File
        6. 9.6. Summary
        7. 9.7. Exercises
    10. 2. Advanced VerilogTopics
      1. 10. Timing and Delays
        1. 10.1. Types of Delay Models
          1. 10.1.1. Distributed Delay
          2. 10.1.2. Lumped Delay
          3. 10.1.3. Pin-to-Pin Delays
        2. 10.2. Path Delay Modeling
          1. 10.2.1. Specify Blocks
          2. 10.2.2. Inside Specify Blocks
            1. Parallel connection
            2. Full connection
            3. Edge-Sensitive Paths
            4. specparam statements
            5. Conditional path delays
            6. Rise, fall, and turn-off delays
            7. Min, max, and typical delays
            8. Handling x transitions
        3. 10.3. Timing Checks
          1. 10.3.1. $setup and $hold Checks
            1. $setup task
            2. $hold task
          2. 10.3.2. $width Check
        4. 10.4. Delay Back-Annotation
        5. 10.5. Summary
        6. 10.6. Exercises
      2. 11. Switch-Level Modeling
        1. 11.1. Switch-Modeling Elements
          1. 11.1.1. MOS Switches
          2. 11.1.2. CMOS Switches
          3. 11.1.3. Bidirectional Switches
          4. 11.1.4. Power and Ground
          5. 11.1.5. Resistive Switches
          6. 11.1.6. Delay Specification on Switches
            1. MOS and CMOS switches
            2. Bidirectional pass switches
            3. Specify blocks
        2. 11.2. Examples
          1. 11.2.1. CMOS Nor Gate
          2. 11.2.2. 2-to-1 Multiplexer
          3. 11.2.3. Simple CMOS Latch
        3. 11.3. Summary
        4. 11.4. Exercises
      3. 12. User-Defined Primitives
        1. 12.1. UDP basics
          1. 12.1.1. Parts of UDP Definition
          2. 12.1.2. UDP Rules
        2. 12.2. Combinational UDPs
          1. 12.2.1. Combinational UDP Definition
          2. 12.2.2. State Table Entries
          3. 12.2.3. Shorthand Notation for Don't Cares
          4. 12.2.4. Instantiating UDP Primitives
          5. 12.2.5. Example of a Combinational UDP
        3. 12.3. Sequential UDPs
          1. 12.3.1. Level-Sensitive Sequential UDPs
          2. 12.3.2. Edge-Sensitive Sequential UDPs
          3. 12.3.3. Example of a Sequential UDP
        4. 12.4. UDP Table Shorthand Symbols
        5. 12.5. Guidelines for UDP Design
        6. 12.6. Summary
        7. 12.7. Exercises
      4. 13. Programming Language Interface
        1. 13.1. Uses of PLI
        2. 13.2. Linking and Invocation of PLI Tasks
          1. 13.2.1. Linking PLI Tasks
          2. 13.2.2. Invoking PLI Tasks
          3. 13.2.3. General Flow of PLI Task Addition and Invocation
        3. 13.3. Internal Data Representation
        4. 13.4. PLI Library Routines
          1. 13.4.1. Access Routines
            1. Mechanics of access routines
            2. Types of access routines
            3. Examples of access routines
          2. 13.4.2. Utility Routines
            1. Mechanics of utility routines
            2. Types of utility routines
            3. Example of utility routines
        5. 13.5. Summary
        6. 13.6. Exercises
      5. 14. Logic Synthesis with Verilog HDL
        1. 14.1. What Is Logic Synthesis?
        2. 14.2. Impact of Logic Synthesis
        3. 14.3. Verilog HDL Synthesis
          1. 14.3.1. Verilog Constructs
          2. 14.3.2. Verilog Operators
          3. 14.3.3. Interpretation of a Few Verilog Constructs
            1. The assign statement
            2. The if-else statement
            3. The case statement
            4. for loops
            5. The function statement
        4. 14.4. Synthesis Design Flow
          1. 14.4.1. RTL to Gates
            1. RTL description
            2. Translation
            3. Unoptimized intermediate representation
            4. Logic optimization
            5. Technology mapping and optimization
            6. Technology library
            7. Design constraints
            8. Optimized gate-level description
          2. 14.4.2. An Example of RTL-to-Gates
            1. Design specification
            2. RTL description
            3. Technology library
            4. Design constraints
            5. Logic synthesis
            6. Final, Optimized, Gate-Level Description
            7. IC Fabrication
        5. 14.5. Verification of Gate-Level Netlist
          1. 14.5.1. Functional Verification
            1. Timing verification
        6. 14.6. Modeling Tips for Logic Synthesis
          1. 14.6.1. Verilog Coding Style
            1. Use meaningful names for signals and variables
            2. Avoid mixing positive and negative edge-triggered flipflops
            3. Use basic building blocks vs. use continuous assign statements
            4. Instantiate multiplexers vs. Use if-else or case statements
            5. Use parentheses to optimize logic structure
            6. Use arithmetic operators *, /, and % vs. Design building blocks
            7. Be careful with multiple assignments to the same variable
            8. Define if-else or case statements explicitly
          2. 14.6.2. Design Partitioning
            1. Horizontal partitioning
            2. Vertical Partitioning
            3. Parallelizing design structure
          3. 14.6.3. Design Constraint Specification
        7. 14.7. Example of Sequential Circuit Synthesis
          1. 14.7.1. Design Specification
          2. 14.7.2. Circuit Requirements
          3. 14.7.3. Finite State Machine (FSM)
          4. 14.7.4. Verilog Description
          5. 14.7.5. Technology Library
          6. 14.7.6. Design Constraints
          7. 14.7.7. Logic Synthesis
          8. 14.7.8. Optimized Gate-Level Netlist
          9. 14.7.9. Verification
          10. 14.8. Summary
        8. 14.9. Exercises
      6. 15. Advanced Verification Techniques
        1. 15.1. Traditional Verification Flow
          1. 15.1.1. Architectural Modeling
          2. 15.1.2. Functional Verification Environment
          3. 15.1.3. Simulation
            1. Software Simulation
            2. Hardware Acceleration
            3. Hardware Emulation
          4. 15.1.4. Analysis
          5. 15.1.5. Coverage
            1. Structural Coverage
            2. Functional Coverage
        2. 15.2. Assertion Checking
        3. 15.3. Formal Verification
          1. 15.3.1. Semi-formal Verification
          2. 15.3.2. Equivalence Checking
        4. 15.4. Summary
    11. 3. Appendices
      1. A. Strength Modeling and Advanced Net Definitions
        1. A.1. Strength Levels
        2. A.2. Signal Contention
          1. A.2.1. Multiple Signals with Same Value and Different Strength
          2. A.2.2. Multiple Signals with Opposite Value and Same Strength
        3. A.3. Advanced Net Types
          1. A.3.1. tri
          2. A.3.2. trireg
          3. A.3.3. tri0 and tri1
          4. A.3.4. supply0 and supply1
          5. A.3.5. wor, wand, trior, and triand
      2. B. List of PLI Routines
        1. B.1. Conventions
        2. B.2. Access Routines
          1. B.2.1. Handle Routines
          2. B.2.2. Next Routines
          3. B.2.3. Value Change Link (VCL) Routines
          4. B.2.4. Fetch Routines
          5. B.2.5. Utility Access Routines
          6. B.2.6. Modify Routines
        3. B.3. Utility (tf_) Routines
          1. B.3.1. Get Calling Task/Function Information
          2. B.3.2. Get Argument List Information
          3. B.3.3. Get Parameter Values
          4. B.3.4. Put Parameter Value
          5. B.3.5. Monitor Parameter Value Changes
          6. B.3.6. Synchronize Tasks
          7. B.3.7. Long Arithmetic
          8. B.3.8. Display Messages
          9. B.3.9. Miscellaneous Utility Routines
          10. B.3.10. Housekeeping Tasks
      3. C. List of Keywords, System Tasks, and Compiler Directives
        1. C.1. Keywords
        2. C.2. System Tasks and Functions
        3. C.3. Compiler Directives
      4. D. Formal Syntax Definition
        1. D.1. Source Text
          1. D.1.1. Library Source Text
          2. D.1.2. Configuration Source Text
          3. D.1.3. Module and Primitive Source Text
          4. D.1.4. Module Parameters and Ports
          5. D.1.5. Module Items
        2. D.2. Declarations
          1. D.2.1. Declaration Types
            1. Module parameter declarations
            2. Port declarations
            3. Type declarations
          2. D.2.2. Declaration Data Types
            1. Net and variable types
            2. Strengths
            3. Delays
          3. D.2.3. Declaration Lists
          4. D.2.4. Declaration Assignments
          5. D.2.5. Declaration Ranges
          6. D.2.6. Function Declarations
          7. D.2.7. Task Declarations
          8. D.2.8. Block Item Declarations
        3. D.3. Primitive Instances
          1. D.3.1. Primitive Instantiation and Instances
          2. D.3.2. Primitive Strengths
          3. D.3.3. Primitive Terminals
          4. D.3.4. Primitive Gate and Switch Types
        4. D.4. Module and Generated Instantiation
          1. D.4.1. Module Instantiation
          2. D.4.2. Generated Instantiation
        5. D.5. UDP Declaration and Instantiation
          1. D.5.1. UDP Declaration
          2. D.5.2. UDP Ports
          3. D.5.3. UDP Body
          4. D.5.4. UDP Instantiation
        6. D.6. Behavioral Statements
          1. D.6.1. Continuous Assignment Statements
          2. D.6.2. Procedural Blocks and Assignments
          3. D.6.3. Parallel and Sequential Blocks
          4. D.6.4. Statements
          5. D.6.5. Timing Control Statements
          6. D.6.6. Conditional Statements
          7. D.6.7. Case Statements
          8. D.6.8. Looping Statements
          9. D.6.9. Task Enable Statements
        7. D.7. Specify Section
          1. D.7.1. Specify Block Declaration
          2. D.7.2. Specify Path Declarations
          3. D.7.3. Specify Block Terminals
          4. D.7.4. Specify Path Delays
          5. D.7.5. System Timing Checks
            1. System timing check commands
            2. System timing check command arguments
            3. System timing check event definitions
        8. D.8. Expressions
          1. D.8.1. Concatenations
          2. D.8.2. Function calls
          3. D.8.3. Expressions
          4. D.8.4. Primaries
          5. D.8.5. Expression Left-Side Values
          6. D.8.6. Operators
          7. D.8.7. Numbers
          8. D.8.8. Strings
        9. D.9. General
          1. D.9.1. Attributes
          2. D.9.2. Comments
          3. D.9.3. Identifiers
          4. D.9.4. Identifier Branches
          5. D.9.5. Whitespace
        10. Endnotes
      5. E. Verilog Tidbits
        1. Origins of Verilog HDL
        2. Interpreted, Compiled, Native Compiled Simulators
        3. Event-Driven Simulation, Oblivious Simulation
        4. Cycle-Based Simulation
        5. Fault Simulation
        6. General Verilog Web sites
        7. Architectural Modeling Tools
        8. High-Level Verification Languages
        9. Simulation Tools
        10. Hardware Acceleration Tools
        11. In-Circuit Emulation Tools
        12. Coverage Tools
        13. Assertion Checking Tools
        14. Equivalence Checking Tools
        15. Formal Verification Tools
      6. F. Verilog Examples
        1. F.1. Synthesizable FIFO Model
          1. Input ports
          2. Output ports
        2. F.2. Behavioral DRAM Model
          1. Input ports
          2. Inout ports
    12. Bibliography
      1. Manuals
      2. Books
      3. Quick Reference Guides
    13. About the CD-ROM
      1. Using the CD-ROM
      2. Technical Support

    Product information

    • Title: Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition
    • Author(s): Samir Palnitkar
    • Release date: February 2003
    • Publisher(s): Pearson
    • ISBN: 9780130449115