Book description
Provides a practical approach to Verilog design and problem solving.
Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
Includes over 90 design examples.
There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
Book is suitable for use as a textbook in EE departments that have VLSI courses
Table of contents
- Cover Page
- Title Page
- Copyright
- Dedication
- Contents
- Table of Figures
- Table Of Examples
- List Of Tables
- Preface
- Acknowledgments
- Trademarks
- CHAPTER ONE: Introduction
- CHAPTER TWO: ASIC Design Flow
- CHAPTER THREE: Verilog Coding
- CHAPTER FOUR: Coding Style: Best-Known Method for Synthesis
- CHAPTER FIVE: Design Example of Programmable Timer
-
CHAPTER SIX: Design Example of Programmable Logic Block for Peripheral Interface
- 6.1 PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE DESIGN SPECIFICATION
- 6.2 MODE OF OPERATION FOR PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE
- 6.3 MICRO-ARCHITECTURE DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE
- 6.4 FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE
- 6.5 SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE PERIPHERAL INTERFACE
- 6.6 SIMULATION FOR PROGRAMMABLE PERIPHERAL INTERFACE DESIGN
- Appendix
- Glossary
- Bibliography
- Index
Product information
- Title: Verilog Coding for Logic Synthesis
- Author(s):
- Release date: April 2003
- Publisher(s): Wiley-Interscience
- ISBN: 9780471429760
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