The Unabridged Pentium 4 IA32 Processor Genealogy

The μop Pipeline

Introduction

The μop pipeline is the path that μops follow as they make their way through the processor core to be executed and then retired.

The P6 Processor's Instruction Pipeline

The μop pipeline in the P6 processor family (see Figure 35-2 on page 845) consisted of 10 stages divided into three sections:

• The in-order front end of the pipeline. Guided by the processor's Branch Prediction logic, the IA32 instructions that comprise the currently executing program are fetched from memory (line-by-line) and are decoded in program order. The resulting μops are queued in strict program order. If any μop references one or more of the GPRs, those references are tagged to point to one or more of the processor's Alias Registers rather ...