Paging Enhancements
PAE-36 Mode
The Problem
Refer to Figure 24-1 on page 555. When any IA32 processor is using the 386 compatible Paging mechanism (described in “386 Demand Mode Paging” on page 209), a 2-level lookup is performed to translate the 32-bit linear address into the 32-bit physical memory address. The linear memory address to be accessed is, by definition, a 32-bit address identifying the target location to be accessed within the currently executing task's 4GB virtual memory address space. The 2-level lookup selects a PTE and, assuming that the PTE's Present bit = 1, the PTE's upper 20 bits supplies the upper 20 bits of the 32-bit physical memory address that will be accessed. The lower 12 bits of the linear address is also used as ...
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