The Designer's Guide to the Cortex-M Processor Family, 2nd Edition

The Designer's Guide to the Cortex-M Processor Family, 2nd Edition

by Trevor Martin
Released June 2016
Publisher(s): Newnes
ISBN: 9780081006344

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Book description

The Designer’s Guide to the Cortex-M Microcontrollers gives you an easy-to-understand introduction to the concepts required to develop programs in C with a Cortex-M based microcontroller. The book begins with an overview of the Cortex-M family, giving architectural descriptions supported with practical examples, enabling you to easily develop basic C programs to run on the Cortex-M0/M0+/M3 and M4 and M7. It then examines the more advanced features of the Cortex architecture such as memory protection, operating modes, and dual stack operation.

Once a firm grounding in the Cortex-M processor has been established the book introduces the use of a small footprint RTOS and the CMSIS-DSP library. The book also examines techniques for software testing and code reuse specific to Cortex-M microcontrollers. With this book you will learn: the key differences between the Cortex-M0/M0+/M3 and M4 and M7; how to write C programs to run on Cortex-M based processors; how to make the best use of the CoreSight debug system; the Cortex-M operating modes and memory protection; advanced software techniques that can be used on Cortex-M microcontrollers; how to use a Real Time Operating System with Cortex-M devices; how to optimize DSP code for the Cortex-M4; and how to build real time DSP systems.

  • Includes an update to the latest version (5) of MDK-ARM, which introduces the concept of using software device packs and software components
  • Includes overviews of the new CMSIS specifications
  • Covers developing software with CMSIS-RTOS showing how to use RTOS in a real world design
  • Provides a new chapter on the Cortex-M7 architecture covering all the new features
  • Includes a new chapter covering test driven development for Cortex-M microcontrollers
  • Features a new chapter on creating software components with CMSIS-Pack and device abstraction with CMSIS-Driver
  • Features a new chapter providing an overview of the ARMv8-M architecture including the TrustZone hardware security model

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. Foreword
  7. Preface
  8. Acknowledgments
  9. Chapter 1. Introduction to the Cortex-M Processor Family
    1. Abstract
    2. Cortex Profiles
    3. Cortex-M3
    4. Advanced Architectural Features
    5. Cortex-M0
    6. Cortex-M0+
    7. Cortex-M4
    8. DSP Instructions
    9. Cortex-M7
    10. Conclusion
  10. Chapter 2. Developing Software for the Cortex-M Family
    1. Abstract
    2. Introduction
    3. Keil Microcontroller Development Kit
    4. Software Packs
    5. The Tutorial Exercises
    6. Installation
    7. Exercise 2.1 Building a First Program
    8. The Blinky Project
    9. Project Configuration
    10. Exercise 2.2 Hardware Debug
    11. Conclusion
  11. Chapter 3. Cortex-M Architecture
    1. Abstract
    2. Introduction
    3. Cortex-M Instruction Set
    4. Programmer’s Model and CPU Registers
    5. Program Status Register
    6. Q Bit and Saturated Maths Instructions
    7. Interrupts and Multicycle Instructions
    8. Conditional Execution—If Then Blocks
    9. Exercise 3.1 Saturated Maths and Conditional Execution
    10. Cortex-M Memory Map and Busses
    11. Write Buffer
    12. Memory Barrier Instructions
    13. System Control Block
    14. Bit Manipulation
    15. Exercise 3.2 Bit Banding
    16. Dedicated Bit Manipulation Instructions
    17. SysTick Timer
    18. Nested Vector Interrupt Controller
    19. Operating Modes
    20. Interrupt Handling—Entry
    21. Interrupt Handling—Exit
    22. Interrupt Handling—Exit Important!
    23. Exercise 3.3 SysTick Interrupt
    24. Cortex-M Processor Exceptions
    25. Priority and Preemption
    26. Groups and Subgroup
    27. Runtime Priority Control
    28. Exception Model
    29. Exercise 3.3 Working with Multiple Interrupts
    30. Bootloader Support
    31. Exercise 3.4 Bootloader
    32. Power Management
    33. Moving From the Cortex-M3
    34. Cortex-M4
    35. Cortex-M0
    36. Cortex-M0+
    37. Conclusion
  12. Chapter 4. Cortex Microcontroller Software Interface Standard
    1. Abstract
    2. Introduction
    3. CMSIS Specifications
    4. CMSIS-Core
    5. CMSIS-RTOS
    6. CMSIS-DSP
    7. CMSIS-Driver
    8. CMSIS-SVD and DAP
    9. CMSIS-Pack
    10. Foundations of CMSIS
    11. Coding Rules
    12. MISRA-C
    13. CMSIS-Core Structure
    14. Startup Code
    15. System Code
    16. Device Header File
    17. CMSIS-Core Header Files
    18. Interrupts and Exceptions
    19. Exercise 4.1 CMSIS and User Code Comparison
    20. CMSIS-Core CPU Intrinsic Instructions
    21. Exercise 4.2 Intrinsic Bit Manipulation
    22. CMSIS-SIMD Intrinsics
    23. CMSIS-Core Debug Functions
    24. CMSIS-Core Functions for Corex-M7
    25. Conclusion
  13. Chapter 5. Advanced Architecture Features
    1. Abstract
    2. Introduction
    3. Cortex Processor Operating Modes
    4. Exercise 5.1 Stack Configuration
    5. Supervisor Call
    6. Exercise 5.2 Supervisor Call
    7. PEND_SV Exception
    8. Example Pend_SV
    9. Interprocessor Events
    10. Exclusive Access
    11. Exercise 5.4 Exclusive Access
    12. Memory Protection Unit
    13. Configuring the MPU
    14. Exercise 5.5 MPU Configuration
    15. MPU Subregions
    16. MPU Limitations
    17. AHB Lite Bus Interface
    18. Conclusion
  14. Chapter 6. Cortex-M7 Processor
    1. Abstract
    2. Superscalar Architecture
    3. Branch Prediction
    4. Exercise 6.1 Simple Loop
    5. Bus Structure
    6. Memory Hierarchy
    7. Exercise 6.2 Locating Code and Data into the TCM
    8. Cache Units
    9. Cache Operation
    10. Instruction Cache
    11. Exercise 6.3 Instruction Cache
    12. Data Cache
    13. Memory Barriers
    14. Exercise 6.4 Example Data Cache
    15. Memory Protection Unit and Cache Configuration
    16. Cache Policy
    17. Managing the Data Cache
    18. Exercise 6.5 Data Cache Configuration
    19. Double Precision Floating Point Unit
    20. Functional Safety
    21. Cortex-M7 Safety Features
    22. Safety Documentation
    23. Development Tools
    24. Conclusion
  15. Chapter 7. Debugging with CoreSight
    1. Abstract
    2. Introduction
    3. CoreSight Hardware
    4. Debugger Hardware
    5. CoreSight Debug Architecture
    6. Exercise 7.1 CoreSight Debug
    7. Hardware Configuration
    8. Software Configuration
    9. Debug Limitations
    10. Instrumentation Trace
    11. Exercise 7.2 Setting Up the ITM
    12. System Control Block Debug Support
    13. Tracking Faults
    14. Exercise 7.3 Processor Fault Exceptions
    15. Instruction Trace with the Embedded Trace Macrocell
    16. Exercise 7.4 Using the ETM Trace
    17. CMSIS-DAP
    18. Cortex-M0+ MTB
    19. Exercise 7.5 Micro Trace Buffer
    20. CMSIS System Viewer Description
    21. Exercise 7.6 CMSIS-SVD
    22. Conclusion Debug Features Summary
  16. Chapter 8. Practical DSP for Cortex-M4 and Cortex-M7
    1. Abstract
    2. Introduction
    3. Hardware FPU
    4. FPU Integration
    5. FPU Registers
    6. Cortex-M7 FPU
    7. Enabling the FPU
    8. Exceptions and the FPU
    9. Using the FPU
    10. Exercise 8.1 Floating Point Unit
    11. Cortex-M4/M7 DSP and SIMD Instructions
    12. Exercise 8.2 SIMD Instructions
    13. Exercise 8.3 Optimizing DSP Algorithms
    14. The CMSIS-DSP Library
    15. CMSIS-DSP Library Functions
    16. Exercise 8.3 Using the CMSIS-DSP Library
    17. DSP Data Processing Techniques
    18. Exercise 8.4 FIR Filter with Block Processing
    19. Fixed Point DSP with Q Numbers
    20. Exercise 8.5 Fixed Point FFT Transform
    21. Conclusion
  17. Chapter 9. Cortex Microcontroller Software Interface Standard-Real-Time Operating System
    1. Abstract
    2. Introduction
    3. First Steps with CMSIS-RTOS
    4. Accessing the CMSIS-RTOS API
    5. Threads
    6. Starting the RTOS
    7. Exercise 9.1 A First CMSIS-RTOS Project
    8. Creating Threads
    9. Exercise 9.2 Creating and Managing Threads
    10. Thread Management and Priority
    11. Exercise 9.3 Creating and Managing Threads II
    12. Multiple Instances
    13. Exercise 9.4 Multiple Thread Instances
    14. Time Management
    15. Time Delay
    16. Waiting for an Event
    17. Exercise 9.5 Time Management
    18. Virtual Timers
    19. Exercise 9.6 Virtual Timer
    20. Sub-Millisecond Delays
    21. Idle Demon
    22. Exercise 9.7 Idle Thread
    23. Inter-Thread Communication
    24. Signals
    25. Exercise 9.8 Signals
    26. Semaphores
    27. Exercise 9.9 Semaphore Signaling
    28. Using Semaphores
    29. Signaling
    30. Multiplex
    31. Exercise 9.10 Multiplex
    32. Rendezvous
    33. Exercise 9.11 Rendezvous
    34. Barrier Turnstile
    35. Exercise 9.12 Semaphore Barrier
    36. Semaphore Caveats
    37. Mutex
    38. Exercise 9.13 Mutex
    39. Mutex Caveats
    40. Data Exchange
    41. Message Queue
    42. Exercise 9.14 Message Queue
    43. Memory Pool
    44. Exercise 9.15 Memory Pool
    45. Mail Queue
    46. Exercise 9.16 Mailbox
    47. Configuration
    48. Thread Definition
    49. Kernel Debug Support
    50. System Timer Configuration
    51. Timeslice Configuration
    52. Scheduling Options
    53. RTX Source Code
    54. RTX License
    55. Conclusion
  18. Chapter 10. RTOS Techniques
    1. Abstract
    2. Introduction
    3. RTOS and Interrupts
    4. RTOS Interrupt Handling
    5. Exercise 10.1 RTOS Interrupt Exercise Handling
    6. User Supervisor Functions
    7. Exercise 10.2 RTOS and User SVC Exceptions
    8. Power Management
    9. Power Management First Steps
    10. Power Management Strategy
    11. Watchdog Management
    12. Integrating ISRs
    13. Exercise 10.3 Power and Watchdog Management
    14. Startup Barrier
    15. Designing for Real Time
    16. Exercise 10.4 RTX Real Time
    17. Shouldering the Load, the Direct Memory Access Controller
    18. Designing for Debug
    19. Exercise 10.5 Run-Time Diagnostics
    20. Conclusion
  19. Chapter 11. Test Driven Development
    1. Abstract
    2. Introduction
    3. Installing the Unity Framework
    4. Exercise 11.1 Test Driven Development
    5. Testing RTOS Threads
    6. Exercise 11.2 Testing RTOS Threads
    7. Exercise 11.3 Testing with Interrupts
    8. Conclusion
  20. Chapter 12. Software Components
    1. Abstract
    2. Introduction
    3. CMSIS Driver
    4. Driver Validation
    5. Designing a Software Component
    6. Creating a Software Pack
    7. Configuration Wizard
    8. Deploying Software Components
    9. Conclusion
  21. Chapter 13. ARMv8-M
    1. Abstract
    2. Introduction
    3. Common Architectural Enhancements
    4. ARMv8 Baseline Enhancements
    5. ARMv8-M Mainline Enhancements
    6. TrustZone
    7. Software Development
    8. Conclusion
  22. Appendix
    1. Contact Details
    2. Appendices
    3. Debug Tools and Software
    4. Real-Time Operating Systems
    5. Books
    6. Cortex-M Processor
    7. Standards
    8. Digital Signal Processing
    9. Real-Time Operating System
    10. Silicon Vendors
    11. Training
  23. Index

Product information

  • Title: The Designer's Guide to the Cortex-M Processor Family, 2nd Edition
  • Author(s): Trevor Martin
  • Release date: June 2016
  • Publisher(s): Newnes
  • ISBN: 9780081006344