RapidIO: The Next Generation Communication Fabric For Embedded Application

Appendix B. Serial Physical Layer Registers

This section specifies the 1×/4× LP-Serial Command and Status Register (CSR) set. All registers in the set are 32 bits long and aligned to a 32-bit boundary. These registers allow an external processing element to determine the capabilities, configuration, and status of a processing element using this 1×/4× LP-Serial physical layer. The registers can be accessed using the maintenance operations defined in Chapter 3.

These registers are located in the 1×/4× LP-Serial physical features block, which is an extended features block in the extended features space. The block may exist in any position in the extended features data structure and may exist in any portion of the extended features address space implemented by a device. (The extended features space is located at byte offsets 0×0100 through 0×FFFC of the device configuration space.)

Register offsets into the block that are not defined are reserved unless otherwise stated. Read and write accesses to reserved register offsets shall terminate normally and shall not cause an error condition in the target device.

This appendix specifies only the registers and register bits that comprise the 1×/4× LP-Serial Command and Status Register set. Refer to the other appendices for the specification of the complete set of registers and register bits required for a given device.

Table B.1 describes the required behavior for accesses to reserved register bits and reserved registers for the RapidIO ...