PCI Express System Architecture

Introduction

The discussions associated with Figure 19-1 on page 713 and Figure 20-4 on page 730 assumed that, each of the buses had been discovered and numbered earlier in time.

In reality, at power up time, the configuration software only knows of the existence of bus 0 (the bus that resides on the downstream side of the Host/PCI bridge) and does not even know what devices reside on bus 0 (see Figure 21-1 on page 742).

Figure 21-1. Topology View At Startup

This chapter describes the enumeration process: the process of discovering the various buses that exist and the devices and functions which reside on each of them.