Network Infrastructure and Architecture: Designing High-Availability Networks

11

PACKET AND CELL SWITCHING AND QUEUING

11.1 Introduction

11.2 Packet–Cell Switching Problem

11.3 Traffic Patterns

11.3.1 Realistic Loads

11.3.2 Responses to Congestion

11.4 Logical Queue Structures and their Behavior

11.4.1 Queues

11.4.2 Flows and Logical Queues

11.4.3 Queuing Systems

11.4.4 Speedup and Blocking

11.4.5 Possible Queuing Systems

11.5 Queue Locations and Buffer Sharing

11.6 Filling and Draining Queues

11.6.1 Filling

11.6.2 Draining

11.7 Central Memory Packet–Cell Switches

11.8 Ingress Buffered Packet–Cell Switches

11.8.1 Blocking Ingress-Buffered Frame Switches

11.8.2 Nonblocking Ingress-Buffered Frame Switches

11.9 Request–Grant Cell Switches

11.9.1 Use of Cells

11.9.2 Request–Grant Protocol

11.9.3 Permutation Arbitration by Wavefront Computation

11.10 Sliced Request–Grant Switches

11.11 Multistage Frame Networks

11.12 Multicast

11.12.1 Multicast in the Blocking Ingress–Buffered Architecture

11.12.2 Multicast in the Nonblocking Ingress–Buffered Architecture

11.12.3 Multicast in the Request–Grant Architecture

Key Points

11.1 INTRODUCTION

This chapter is the third in a sequence of three chapters on switching technologies. In Chapter 9 are provided an overview of switching issues and considered the switching of complete physical signals. In Chapter 10 we examined the switching of logical channel [or time-division-multiplexed (TDM)] signals such as SONET/SDH. This chapter covers the switching of packets and cells. After briefly defining the packet–cell switching problem, ...