Mobile 3D Graphics SoC: From Algorithm to Chip

7

Low-power Rasterizer Design

This chapter attempts to show how to design a large-scale system – from specification to real implementation – by means of an example of a low-power rasterizer. First, high-level information about the rasterizer is described: its target system architecture, performance and feature summaries, and instruction set architecture. We explain the details of the rasterizer from top module to tiny single register. We also include the verilog source codes. The source code and simulation environments are included on the CD accompanying this book.

7.1 Target System Architecture

When you start to design a certain functional unit, the most important thing is to define the target system. You need to define the boundary conditions such as power, memory bandwidth, and job partitioning from the system's view, otherwise the unit you design may not provide the desired performance in the system. In this chapter we assume that the rasterizer is connected to the system using memory-mapped I/O. The application software and geometry operations are computed in the host processor, and the rasterizer performs the remaining rendering operation, shading and texturing. Figure 7.1 shows the target system architecture including the rasterizer.

The host processor performs geometry operations using primitive data stored in system memory. The vertex data and rendering commands are transferred to the rendering processor through the system bus. The rendering processor generates texture-mapped ...