Microprocessors and Microcomputer-Based System Design, 2nd Edition

Microprocessors and Microcomputer-Based System Design, 2nd Edition

by Mohamed Rafiquzzaman
Released November 2021
Publisher(s): CRC Press
ISBN: 9781000141467

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Book description

Microprocessors and Microcomputer-Based System Design, Second Edition discusses the basics of microprocessors, various 32-bit microprocessors, the 8085 microprocessor, the fundamentals of peripheral interfacing, and Intel and Motorola microprocessors. This edition includes topics such as floating-point arithmetic, Program Array Logic, and flash mem

Table of contents

  1. Cover
  2. Title Page
  3. Copyright Page
  4. Preface
  5. The Author
  6. Dedication
  7. Table of Contents
  8. Chapter 1 Introduction to Microprocessors and Microcomputer-Based Applications
    1. 1.1 Evolution of the Microprocessor
    2. 1.2 Microprocessor Data Types
      1. 1.2.1 Unsigned and Signed Binary Integers
      2. 1.2.2 BCD (Binary Coded Decimal) Numbers
      3. 1.2.3 ASCII
      4. 1.2.4 Floating-Point Numbers
    3. 1.3 Microcomputer Hardware
      1. 1.3.1 The System Bus
      2. 1.3.2 The Microprocessor
      3. 1.3.3 Memory Organization
        1. 1.3.3.a Introduction
        2. 1.3.3.b Main Memory Array Design
        3. 1.3.3.c Memory Management Concepts
        4. 1.3.3.d Cache Memory Organization
      4. 1.3.4 Input/Output (I/O)
        1. 1.3.4.a Programmed I/O
        2. 1.3.4.b Standard I/O Versus Memory-Mapped I/O
        3. 1.3.4.c Unconditional and Conditional Programmed I/O
        4. 1.3.4.d Typical Microcomputer Output Circuit
        5. 1.3.4.e Interrupt Driven I/O
        6. 1.3.4.f Direct Memory Access (DMA)
        7. 1.3.4.g Summary of Microcomputer I/O Methods
        8. 1.3.4.h Coprocessors
    4. 1.4 Microcomputer System Software and Programming Concepts
      1. 1.4.1 System Software
      2. 1.4.2 Programming Concepts
        1. 1.4.2.a Assembly Language Programming
        2. 1.4.2.b High-Level Language Programming
        3. 1.4.2.c Which Programming Language to Choose?
    5. 1.5 Typical Microcomputer Addressing Modes and Instructions
      1. 1.5.1 Introduction
      2. 1.5.2 Addressing Modes
      3. 1.5.3 Instruction Types
    6. 1.6 Basic Features of Microcomputer Development Systems
    7. 1.7 System Development Flowchart
      1. 1.7.1 Software Development
      2. 1.7.2 Hardware Development
    8. 1.8 Typical Microprocessors
    9. 1.9 Typical Practical Applications
      1. 1.9.1 Personal Workstations
      2. 1.9.2 Fault-Tolerant Systems
      3. 1.9.3 Real-Time Controllers
      4. 1.9.4 Robotics
      5. 1.9.5 Embedded Control
  9. Chapter 2 Intel
    1. 2.1 Introduction
    2. 2.2 Register Architecture
    3. 2.3 Memory Addressing
    4. 2.4 8085 Addressing Modes
    5. 2.5 8085 Instruction Set
    6. 2.6 Timing Methods
    7. 2.7 8085 Pins and Signals
    8. 2.8 8085 Instruction Timing and Execution
      1. 2.8.1 Basic System Timing
      2. 2.8.2 8085 Memory READ (IO/M = 0, RD = 0) and I/O READ (IO/M = 1, RD =_0)
      3. 2.8.3 8085 Memory WRITE (IO/M = 0, WR = 0) and I/O WRITE (IO/M = 1, WR = 0)
    9. 2.9 8085 Input/Output (I/O)
      1. 2.9.1 8085 Programmed I/O
        1. 2.9.1.a 8355/8755 I/O Ports
        2. 2.9.1.b 8155/8156 I/O Ports
      2. 2.9.2 8085 Interrupt System
      3. 2.9.3 8085 DMA
      4. 2.9.4 8085 SID and SOD Lines
    10. 2.10 8085-Based System Design
    11. Questions and Problems
  10. Chapter 3 Intel 8086
    1. 3.1 Introduction
    2. 3.2 8086 Architecture
    3. 3.3 8086 Addressing Modes
      1. 3.3.1 Addressing Modes for Accessing Immediate and Register Data (Register and Immediate Modes)
        1. 3.3.1.a Register Addressing Mode
        2. 3.3.1.b Immediate Addressing Mode
      2. 3.3.2 Addressing Modes for Accessing Data in Memory (Memory Modes)
        1. 3.3.2.a Direct Addressing Mode
        2. 3.3.2.b Register Indirect Addressing Mode
        3. 3.3.2.c Based Addressing Mode
        4. 3.3.2.d Indexed Addressing Mode
        5. 3.3.2.e Based Indexed Addressing Mode
        6. 3.3.2.f String Addressing Mode
      3. 3.3.3 Addressing Modes for Accessing I/O Ports (I/O Modes)
      4. 3.3.4 Relative Addressing Mode
      5. 3.3.5 Implied Addressing Mode
    4. 3.4 8086 Instruction Set
    5. 3.5 8086 Assembler-Dependent Instructions
    6. 3.6 ASM-86 Assembler Directives
      1. 3.6.1 SEGMENT and ENDS Directives
      2. 3.6.2 Assume Directive
      3. 3.6.3 DUP Directive
    7. 3.7 System Design Using the 8086
      1. 3.7.1 Pins and Signals
      2. 3.7.2 8086 Basic System Concepts
        1. 3.7.2.a 8086 Bus Cycle
        2. 3.7.2.b 8086 Address and Data Bus Concepts
      3. 3.7.3 Interfacing with Memories
        1. 3.7.3.a ROM and EPROM
        2. 3.7.3.b Static RAMs
        3. 3.7.3.c Dynamic RAMs
      4. 3.7.4 8086 Programmed I/O
    8. 3.8 8086-Based Microcomputer
    9. 3.9 8086 Interrupt System
      1. 3.9.1 Predefined Interrupts (0 to 4)
      2. 3.9.2 User-Defined Software Interrupts
      3. 3.9.3 User-Defined Hardware (Maskable Interrupts, Type Codes 3210 — 25510)
    10. 3.10 8086 DMA
    11. Questions and Problems
  11. Chapter 4 Intel 80186/80286/80386
    1. 4.1 Intel 80186 and 80286
      1. 4.1.1 Intel 80186
      2. 4.1.2 Intel 80286
        1. 4.1.2.a 80286 Memory Management
        2. 4.1.2.b Protection
        3. 4.1.2.c 80286 Exceptions
    2. 4.2 Intel 80386
      1. 4.2.1 Basic 80386 Programming Model
        1. 4.2.1.a Memory Organization and Segmentation
        2. 4.2.1.b Data Types
        3. 4.2.1.c 80386 Registers
        4. 4.2.1.d 80386 Addressing Modes
      2. 4.2.2 80386 Instruction Set
        1. 4.2.2.a Arithmetic Instructions
        2. 4.2.2.b Bit Manipulation Instructions
        3. 4.2.2.c Byte-Set-On Condition Instructions
        4. 4.2.2.d Conditional Jumps and Loops
        5. 4.2.2.e Data Transfer
        6. 4.2.2.f Flag Control
        7. 4.2.2.g Logical
        8. 4.2.2.h String
        9. 4.2.2.i Table Look-Up Translation Instruction
        10. 4.2.2.j High-Level Language Instructions
      3. 4.2.3 Memory Organization
      4. 4.2.4 I/O Space
      5. 4.2.5 80386 Interrupts
      6. 4.2.6 80386 Reset and Initialization
      7. 4.2.7 Testability
      8. 4.2.8 Debugging
      9. 4.2.9 80386 Pins and Signals
      10. 4.2.10 80386 Bus Transfer Technique
      11. 4.2.11 80386 Read and Write Cycles
      12. 4.2.12 80386 Modes
        1. 4.2.12.a 80386 Real Mode
        2. 4.2.12.b Protected Mode
        3. 4.2.12.c Virtual 8086 Mode
    3. 4.3 80386 System Design
      1. 4.3.1 80386 Memory Interface
      2. 4.3.2 80386 I/O
    4. 4.4 Coprocessor Interface
      1. 4.4.1 Coprocessor Hardware Concepts
      2. 4.4.2 Coprocessor Registers
      3. 4.4.3 80387 Instructions
    5. Questions and Problems
  12. Chapter 5 Motorola MC68000
    1. 5.1 Introduction
    2. 5.2 68000 Programming Model
    3. 5.3 68000 Addressing Structure
    4. 5.4 68000 Addressing Modes
      1. 5.4.1 Register Direct Addressing
      2. 5.4.2 Address Register Indirect Addressing
      3. 5.4.3 Absolute Addressing
      4. 5.4.4 Program Counter Relative Addressing
      5. 5.4.5 Immediate Data Addressing Mode
      6. 5.4.6 Implied Addressing
    5. 5.5 68000 Instruction Set
      1. 5.5.1 Data Movement Instructions
        1. 5.5.1.a MOVE Instructions
        2. 5.5.1.b EXG and SWAP Instructions
        3. 5.5.1.c LEA and PEA Instructions
        4. 5.5.1.d LINK and UNLK Instructions
      2. 5.5.2 Arithmetic Instructions
        1. 5.5.2.a Addition and Subtraction Instructions
        2. 5.5.2.b Multiplication and Division Instructions
        3. 5.5.2.c Compare, Clear, and Negate Instructions
        4. 5.5.2.d Extended Arithmetic Instructions
        5. 5.5.2.e Test Instructions
        6. 5.5.2.f Test and Set Instruction
      3. 5.5.3 Logical Instructions
      4. 5.5.4 Shift and Rotate Instructions
      5. 5.5.5 Bit Manipulation Instructions
      6. 5.5.6 Binary-Coded Decimal Instructions
      7. 5.5.7 Program Control Instructions
      8. 5.5.8 System Control Instructions
    6. 5.6 68000 Stacks
    7. 5.7 68000 Pins and Signals
      1. 5.7.1 Synchronous and Asynchronous Control Lines
      2. 5.7.2 System Control Lines
      3. 5.7.3 Interrupt Control Lines
      4. 5.7.4 DMA Control Lines
      5. 5.7.5 Status Lines
    8. 5.8 68000 System Diagram
    9. 5.9 Timing Diagrams
    10. 5.10 68000 Memory Interface
    11. 5.11 68000 Programmed I/O
      1. 5.11.1 68000-68230 Interface
      2. 5.11.2 Motorola 68000-6821 Interface
    12. 5.12 68000/2716/6116/6821-Based Microcomputer
    13. 5.13 68000 Interrupt I/O
      1. 5.13.1 External Interrupts
      2. 5.13.2 Internal Interrupts
      3. 5.13.3 68000 Exception Map
      4. 5.13.4 68000 Interrupt Address Vector
      5. 5.13.5 An Example of Autovector and Nonautovector Interrupts
    14. 5.14 68000 DMA
    15. 5.15 68000 Exception Handling
    16. 5.16 Multiprocessing with the 68000 Using the TAS Instruction and AS (Address Strobe) Signal
    17. Questions and Problems
  13. Chapter 6 Motorola MC68020
    1. 6.1 Introduction
    2. 6.2 Programming Model
    3. 6.3 Data Types, Organization, and CPU Space Cycle
    4. 6.4 MC68020 Addressing Modes
      1. 6.4.1 Address Register Indirect (ARI) with Index and 8-Bit Displacement
      2. 6.4.2 ARI with Index (Base Displacement, bd: Value 0 or 16 Bits or 32 Bits)
      3. 6.4.3 Memory Indirect
      4. 6.4.4 Memory Indirect with PC
        1. 6.4.4.a PC Indirect with Index (8-Bit Displacement)
        2. 6.4.4.b PC Indirect with Index (Base Displacement)
        3. 6.4.4.c PC Indirect (Postindexed)
        4. 6.4.4.d PC Indirect (Preindexed)
    5. 6.5 68020 Instructions
      1. 6.5.1 New Privileged Move Instruction
      2. 6.5.2 Return and Delocate Instruction
      3. 6.5.3 CHK/CHK2 and CMP/CMP2 Instructions
      4. 6.5.4 Trap On Condition Instructions
      5. 6.5.5 Bit Field Instructions
      6. 6.5.6 Pack and Unpack Instructions
      7. 6.5.7 Multiplication and Division Instructions
      8. 6.5.8 MC68000 Enhanced Instructions
    6. 6.6 68020 Advanced Instructions
      1. 6.6.1 Breakpoint Instruction
      2. 6.6.2 Call Module/Return from Module Instructions
      3. 6.6.3 CAS Instuctions
      4. 6.6.4 Coprocessor Instructions
    7. 6.7 MC68020 Cache/Pipelined Architecture and Operation
    8. 6.8 MC68020 Virtual Memory
    9. 6.9 MC68020 Coprocessor Interface
      1. 6.9.1 MC68881 Floating-Point Coprocessor
        1. 6.9.1.a 68881 Data Movement Instructions
        2. 6.9.1.b Monadic
        3. 6.9.1.c Dyadic Instructions
        4. 6.9.1.d BRANCH, Set, or Trap-On Condition
        5. 6.9.1.e Miscellaneous Instructions
      2. 6.9.2 MC68851 MMU
    10. 6.10 MC68020 Pins and Signals
    11. 6.11 MC68020 Timing Diagrams
    12. 6.12 Exception Processing
    13. 6.13 MC68020 System Design
    14. Questions and Problems
  14. Chapter 7 Motorola MC68030/MC68040, Intel 80486 and Pentium Microprocessors
    1. 7.1 Motorola MC68030
      1. 7.1.1 MC68030 Block Diagram
      2. 7.1.2 MC68030 Programming Model
      3. 7.1.3 MC68030 Data Types, Addressing Modes, and Instructions
        1. 7.1.3.a PMOVE Rn, (EA) or (EA), Rn
        2. 7.1.3.b PTEST
        3. 7.1.3.c PLOAD
        4. 7.1.3.d PFLUSH
      4. 7.1.4 MC68030 Cache
      5. 7.1.5 68030 Pins and Signals
      6. 7.1.6 MC68030 Read and Write Timing Diagrams
      7. 7.1.7 MC68030 On-Chip Memory Management Unit
        1. 7.1.7.a MMU Basics
        2. 7.1.7.b 68030 On-chip MMU
    2. 7.2 MC68040
      1. 7.2.1 Introduction
      2. 7.2.2 Register Architecture/Addressing Modes
      3. 7.2.3 Instruction Set/Data Types
      4. 7.2.4 68040 Processor Block Diagram
      5. 7.2.5 68040 Memory Management
      6. 7.2.6 Discussion and Conclusion
    3. 7.3 Intel 80486 Microprocessor
      1. 7.3.1 Intel 80486/80386 Comparison
      2. 7.3.2 Special Features of the
      3. 7.3.3 80486 New Instructions Beyond Those of the
    4. 7.4 Intel Pentium Microprocessor
      1. 7.4.1 Pentium Processor Block Diagram
      2. 7.4.2 Pentium Registers
      3. 7.4.3 Pentium Addressing Modes and Instructions
      4. 7.4.4 Pentium Vs. 80486 Basic Differences in Registers, Paging, Stack Operations, and Exceptions
        1. 7.4.4.a Registers of the Pentium Processor vs. Those of the
        2. 7.4.4.b Paging
        3. 7.4.4.c Stack Operations
        4. 7.4.4.d Exceptions
      5. 7.4.5 Input/Output
      6. 7.4.6 Applications with the Pentium
    5. Questions and Problems
  15. Chapter 8 RISC Microprocessors: Intel 80960, Motorola MC88100 and PowerPC
    1. 8.1 Basics of RISC
    2. 8.2 Intel
      1. 8.2.1 Introduction
      2. 8.2.2 Key Performance Features
        1. 8.2.2.a Load and Store Model
        2. 8.2.2.b Large Internal Register Sets
        3. 8.2.2.c On-Chip Code and Data Checking
        4. 8.2.2.d Overlapped Instruction Execution
        5. 8.2.2.e Single Clock Instructions
        6. 8.2.2.f Interrupt Model
        7. 8.2.2.g Procedure Call Mechanism
        8. 8.2.2.h Instruction Set and Addressing
        9. 8.2.2.i Floating Point Unit (Available with 80960SB only)
      3. 8.2.3 80960SA/SB Registers
        1. 8.2.3.a Register Scoreboarding
        2. 8.2.3.b Instruction Pointer
        3. 8.2.3.c Process Control Register
        4. 8.2.3.d Arithmetic Control
      4. 8.2.4 Data Types and Addresses
        1. 8.2.4.a Data Types
        2. 8.2.4.b Literals
        3. 8.2.4.c Register Addressing
        4. 8.2.4.d Memory Addressing Modes
      5. 8.2.5 809690SA/SB Instruction Set
        1. 8.2.5.a Data Movement
        2. 8.2.5.b Conversion (Available with 80960SB only)
        3. 8.2.5.c Arithmetic and Logic Operations
        4. 8.2.5.d Comparison and Control
      6. 8.2.6 80960SA/SB Pins and Signals
        1. 8.2.6.a Basic Bus States
        2. 8.2.6.b Signals Groups
      7. 8.2.7 Basic READ and WRITE
      8. 8.2.8 80960SA/SB-Based Microcomputer
    3. 8.3 Motorola MC88100 RISC Microprocessor
      1. 8.3.1 88100/88200 Interface
      2. 8.3.2 88100 Registers
      3. 8.3.3 88100 Data Types, Addressing Modes, and Instructions
      4. 8.3.4 88100 Pins and Signals
      5. 8.3.5 88100 Exception Processing
    4. 8.4 IBM/Motorola/Apple PowerPC
      1. 8.4.1 PowerPC 601 Block Diagram
        1. 8.4.1.a RTC (Real Time Clock)
        2. 8.4.1.b Instruction Unit
        3. 8.4.1.c Execution Unit
        4. 8.4.1.d Memory Management Unit (MMU)
        5. 8.4.1.e Cache Unit :
        6. 8.4.1.f Memory Unit
        7. 8.4.1.g System Interface
      2. 8.4.2 Byte and Bit Ordering
      3. 8.4.3 PowerPC Resigsters and Programming Model
        1. 8.4.3.a User-Level Registers
        2. 8.4.3.b Supervisor-Level Registers
      4. 8.4.4 PowerPC 601 Memory Addressing: Effective Address (EA) Calculation
        1. 8.4.4.a Register Indirect with Immediate Index Mode
        2. 8.4.4.b Register Indirect with Index Mode
      5. 8.4.5 PowerPC 601 Typical Instructions
        1. 8.4.5.a Integer Instructions
        2. 8.4.5.b Floating-Point Instructions
        3. 8.4.5.c Load/Store Instructions
        4. 8.4.5.d Flow Control Instructions
        5. 8.4.5.e Processor Control Instructions
      6. 8.4.6 PowerPC 601 Exception Model
      7. 8.4.7 601 System Interface
        1. 8.4.7.a Memory Accesses
        2. 8.4.7.b I/O Controller Interface Operations
        3. 8.4.7.c 601 Signals
      8. 8.4.8 PowerPC 601 Vs. Alpha
    5. 8.5 64-Bit RISC Microprocessors
    6. Questions and Problems
  16. Chapter 9 Peripheral Interfacing
    1. 9.1 Keyboard Interface
      1. 9.1.1 Basics of Keyboard and Display Interface to a Microprocessor
      2. 9.1.2 8086 Keyboard Interface
        1. 9.1.2.a Hardware
        2. 9.1.2.b Software
    2. 9.2 DMA Controllers
    3. 9.3 Printer Interface
      1. 9.3.1 LRC7040 Printer Interface Using Direct Microcomputer Control
      2. 9.3.2 LRC7040 Printer Interface to a Microcomputer Using the 8295 Printer Controller Chip
        1. 9.3.2.a 8295 Parallel Interface
        2. 9.3.2.b 8295 Serial Mode
    4. 9.4 CRT (Cathode Ray Tube) Controller and Graphics Controller Chips
      1. 9.4.1 CRT Fundamentals
      2. 9.4.2 Intel 8275 CRT Controller
      3. 9.4.3 Intel 82786 Graphics Controller
    5. 9.5 Coprocessors
      1. 9.5.1 Intel 8087
      2. 9.5.2 Intel 80287
      3. 9.5.3 Intel 80387
    6. Questions and Problems
  17. Chapter 10 Design Problems
    1. 10.1 Design Problem No. 1
      1. 10.1.1 Problem Statement
      2. 10.1.2 Objective
      3. 10.1.3 Operation
      4. 10.1.4 Hardware
      5. 10.1.5 Software
    2. 10.2 Design Problem No. 2
      1. 10.2.1 Display Scroller Using the Intel 8086
        1. 10.2.1.a Introduction and Problem Statement
        2. 10.2.1.b Hardware Description
        3. 10.2.1.c Software Development
    3. 10.3 Design Problem No. 3
      1. 10.3.1 Problem Statement
      2. 10.3.2 Solution No. 1
        1. 10.3.2.a Hardware
        2. 10.3.2.b Microcomputer Development System
        3. 10.3.2.c Software
      3. 10.3.3 Solution No. 2
        1. 10.3.3.a Hardware
        2. 10.3.3.b Software
    4. Questions and Problems
  18. Appendix A: The Hewlett-Packard (HP) 64000
  19. Appendix B: Motorola MC68000 and Support Chips — Data Sheets
  20. Appendix C: Intel 8085, 8086, and Support Chips — Data Sheets
  21. Appendix D: MC68000 Instruction Execution Times
  22. Appendix E: 8086 Instruction Set Reference Data
  23. Appendix F: Glossary/ASCII Codes
  24. Bibliography
  25. Credits
  26. Index

Product information

  • Title: Microprocessors and Microcomputer-Based System Design, 2nd Edition
  • Author(s): Mohamed Rafiquzzaman
  • Release date: November 2021
  • Publisher(s): CRC Press
  • ISBN: 9781000141467