Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

2.7 ADDITION OF SIGNED NUMBERS

2.7.1 Addition Using the Sign-Magnitude Method

The addition of signed numbers using the sign-magnitude method is simple if the operands in the addition are of the same sign, wherein the result takes on the sign of the operands. But in case the operands have different signs, the process becomes complicated, and when used in computers it requires logic circuits to compare and subtract the numbers. Since it is possible to carry out the process without this circuitry, this method is not used in computer design.

2.7.2 Addition Using the One's-Complement Method

This method uses the simplicity of one's complement in representing the negative of a number. The process of addition using the one's-complement method may be simple or complicated, depending on the numbers being used. In certain cases, an additional correction may need to be carried out to arrive at the correct answer. The following examples illustrate one's-complement additions for four cases:

These examples show how a correction needs to be used in certain cases to form the result expected. The carryout from the MSB is added to the result to obtain the results expected.

2.7.3 Addition Using the Two's-Complement Method

Using the same examples as above, the two's-complement method is implemented. ...