Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

1.9 FIELD-PROGRAMMABLE GATE ARRAYS

Field-programmable gate arrays (FPGAs) differ from the other PLDs and generally offer the highest logic capacity. An FPGA consists of an array of complex logic blocks (CLBs) surrounded by programmable I/O blocks (IOBs) and connected by a programmable interconnection network. The IOBs provide the control between the input-output package pins and the internal signal lines, and the programmable interconnect resources provide the correct paths to connect the inputs and outputs of CLBs and IOBs into the appropriate networks. The logic cells combinational logic may be implemented physically as a small lookup table memory (LUT) or a set of multiplexers and gates. An LUT is a 1-bit-wide memory array; the memory address lines are logic block inputs and the 1-bit-memory output is the lookup table output.

A typical FPGA may contain tens of thousands of (configurable) logic blocks and an even greater number of flip-flops. The user's logic function is implemented by closing the switches in the interconnect matrix that specify the logic function for each logic cell. Complex designs are then created by combining these basic blocks to create the desired circuit. Typically, FPGAs do not provide a 100% interconnect between logic blocks (Figure 1.3). There are four main categories of FPGAs currently available commercially: symmetrical array, row-based, hierarchical PLD, and sea of gates. Currently, the four technologies in use are static RAM cells, antifuse, EPROM ...