IBM z15 (8561) Technical Guide

IBM z15 (8561) Technical Guide

by Octavian Lascu, John Troy, Jannie Houlbjerg, Frank Packheiser, Paul Schouten, Kazuhiro Nakajima, Anna Shugol, Hervey Kamga, Bo XU
Released May 2024
Publisher(s): IBM Redbooks
ISBN: 9780738458120

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Book description

This IBM® Redbooks® publication describes the features and functions the latest member of the IBM Z® platform, the IBM z15™ (machine type 8561). It includes information about the IBM z15 processor design, I/O innovations, security features, and supported operating systems.

The z15 is a state-of-the-art data and transaction system that delivers advanced capabilities, which are vital to any digital transformation. The z15 is designed for enhanced modularity, which is in an industry standard footprint.

This system excels at the following tasks:


  • Making use of multicloud integration services
  • Securing data with pervasive encryption
  • Accelerating digital transformation with agile service delivery
  • Transforming a transactional platform into a data powerhouse
  • Getting more out of the platform with IT Operational Analytics
  • Accelerating digital transformation with agile service delivery
  • Revolutionizing business processes
  • Blending open source and Z technologies

This book explains how this system uses new innovations and traditional Z strengths to satisfy growing demand for cloud, analytics, and open source technologies. With the z15 as the base, applications can run in a trusted, reliable, and secure environment that improves operations and lessens business risk.

Table of contents

  1. Front cover
  2. Notices
    1. Trademarks
  3. Preface
    1. Authors
    2. Now you can become a published author, too!
    3. Comments welcome
    4. Stay connected to IBM Redbooks
  4. Chapter 1. Introduction
    1. 1.1 Design considerations for the IBM z15
      1. 1.1.1 Complementing and augmenting cloud solutions
      2. 1.1.2 Compliance, resiliency, and performance
      3. 1.1.3 Pervasive encryption
      4. 1.1.4 IBM Z Data Privacy Passports
      5. 1.1.5 Blending open source with IBM Z state-of-the-art technologies
    2. 1.2 z15 server highlights
      1. 1.2.1 Processor and memory
      2. 1.2.2 Capacity and performance
      3. 1.2.3 Virtualization
      4. 1.2.4 I/O subsystem and I/O features
      5. 1.2.5 Reliability, availability, and serviceability design
    3. 1.3 z15 server technical overview
      1. 1.3.1 Model and features
      2. 1.3.2 Model upgrade paths
      3. 1.3.3 Frames
      4. 1.3.4 CPC drawer
      5. 1.3.5 I/O connectivity: PCIe+ Generation 3
      6. 1.3.6 I/O subsystem
      7. 1.3.7 I/O and special purpose features in the PCIe I/O drawer
      8. 1.3.8 Storage connectivity
      9. 1.3.9 Network connectivity
      10. 1.3.10 Coupling and Server Time Protocol connectivity
      11. 1.3.11 Cryptography
    4. 1.4 Reliability, availability, and serviceability
    5. 1.5 Hardware Management Consoles and Support Elements
    6. 1.6 Operating systems
      1. 1.6.1 Supported operating systems
      2. 1.6.2 IBM compilers
  5. Chapter 2. Central processor complex hardware components
    1. 2.1 Frames and configurations
      1. 2.1.1 z15 cover (door) design
      2. 2.1.2 Top exit I/O and cabling
    2. 2.2 CPC drawer
      1. 2.2.1 CPC drawer interconnect topology
      2. 2.2.2 Oscillator
      3. 2.2.3 System control
      4. 2.2.4 CPC drawer power
    3. 2.3 Single chip modules
      1. 2.3.1 Processor unit chip
      2. 2.3.2 Processor unit (core)
      3. 2.3.3 PU characterization
      4. 2.3.4 System Controller chip
      5. 2.3.5 Cache level structure
    4. 2.4 PCIe+ I/O drawer
    5. 2.5 Memory
      1. 2.5.1 Memory subsystem topology
      2. 2.5.2 Redundant array of independent memory
      3. 2.5.3 Memory configurations
      4. 2.5.4 Memory upgrades
      5. 2.5.5 Drawer replacement and memory
      6. 2.5.6 Virtual Flash Memory
      7. 2.5.7 Flexible Memory Option
    6. 2.6 Reliability, availability, and serviceability
      1. 2.6.1 RAS in the CPC memory subsystem
      2. 2.6.2 General z15 T01 RAS features
    7. 2.7 Connectivity
      1. 2.7.1 Redundant I/O interconnect
      2. 2.7.2 Enhanced drawer availability (EDA)
      3. 2.7.3 CPC drawer upgrade
    8. 2.8 Model configurations
      1. 2.8.1 Upgrades
      2. 2.8.2 Model capacity identifier
    9. 2.9 Power and cooling
      1. 2.9.1 PDU-based configurations
      2. 2.9.2 BPA-based configurations
      3. 2.9.3 Internal Battery Feature
      4. 2.9.4 Power estimation tool
      5. 2.9.5 Cooling
      6. 2.9.6 Radiator Cooling Unit
      7. 2.9.7 Water-cooling unit
    10. 2.10 Summary
  6. Chapter 3. Central processor complex design
    1. 3.1 Overview
    2. 3.2 Design highlights
    3. 3.3 CPC drawer design
      1. 3.3.1 Cache levels and memory structure
      2. 3.3.2 CPC drawer interconnect topology
    4. 3.4 Processor unit design
      1. 3.4.1 Simultaneous multithreading
      2. 3.4.2 Single-instruction multiple-data
      3. 3.4.3 Out-of-Order execution
      4. 3.4.4 Superscalar processor
      5. 3.4.5 Compression and cryptography accelerators on a chip
      6. 3.4.6 Decimal floating point accelerator
      7. 3.4.7 IEEE floating point
      8. 3.4.8 Processor error detection and recovery
      9. 3.4.9 Branch prediction
      10. 3.4.10 Wild branch
      11. 3.4.11 Translation lookaside buffer
      12. 3.4.12 Instruction fetching, decoding, and grouping
      13. 3.4.13 Extended Translation Facility
      14. 3.4.14 Instruction set extensions
      15. 3.4.15 Transactional Execution
      16. 3.4.16 Runtime Instrumentation
    5. 3.5 Processor unit functions
      1. 3.5.1 Overview
      2. 3.5.2 Central processors
      3. 3.5.3 Integrated Facility for Linux (FC 1945)
      4. 3.5.4 Internal Coupling Facility (FC 1946)
      5. 3.5.5 IBM Z Integrated Information Processor (FC 1947)
      6. 3.5.6 System assist processors
      7. 3.5.7 Reserved processors
      8. 3.5.8 Integrated firmware processor
      9. 3.5.9 Processor unit assignment
      10. 3.5.10 Sparing rules
      11. 3.5.11 CPC drawer numbering
    6. 3.6 Memory design
      1. 3.6.1 Overview
      2. 3.6.2 Main storage
      3. 3.6.3 Hardware system area
      4. 3.6.4 Virtual Flash Memory (FC 0643)
    7. 3.7 Logical partitioning
      1. 3.7.1 Overview
      2. 3.7.2 Storage operations
      3. 3.7.3 Reserved storage
      4. 3.7.4 Logical partition storage granularity
      5. 3.7.5 LPAR dynamic storage reconfiguration
    8. 3.8 Intelligent Resource Director
    9. 3.9 Clustering technology
      1. 3.9.1 CF Control Code
      2. 3.9.2 Coupling Thin Interrupts
      3. 3.9.3 Dynamic CF dispatching
    10. 3.10 Virtual Flash Memory
      1. 3.10.1 IBM Z Virtual Flash Memory overview
      2. 3.10.2 VFM feature
      3. 3.10.3 VFM administration
    11. 3.11 Secure Service Container
  7. Chapter 4. Central processor complex I/O structure
    1. 4.1 Introduction to I/O infrastructure
      1. 4.1.1 I/O infrastructure
      2. 4.1.2 PCIe Generation 3
    2. 4.2 I/O system overview
      1. 4.2.1 Characteristics
      2. 4.2.2 Supported I/O features
    3. 4.3 PCIe+ I/O drawer
      1. 4.3.1 PCIe+ I/O drawer offerings
    4. 4.4 CPC drawer fanouts
      1. 4.4.1 PCIe+ Generation 3 fanout (FC 0175)
      2. 4.4.2 Integrated Coupling Adapter (FC 0172 and 0176)
      3. 4.4.3 Fanout considerations
    5. 4.5 I/O features
      1. 4.5.1 I/O feature card ordering information
      2. 4.5.2 Physical channel ID report
    6. 4.6 Connectivity
      1. 4.6.1 I/O feature support and configuration rules
      2. 4.6.2 Storage connectivity
      3. 4.6.3 Network connectivity
      4. 4.6.4 Parallel Sysplex connectivity
    7. 4.7 Cryptographic functions
      1. 4.7.1 CPACF functions (FC 3863)
      2. 4.7.2 Crypto Express7S feature (FC 0898 and FC 0899)
      3. 4.7.3 Crypto Express6S feature (FC 0893) as carry forward only
      4. 4.7.4 Crypto Express5S feature (FC 0890) as carry forward only
    8. 4.8 Integrated Firmware Processor
  8. Chapter 5. Central processor complex channel subsystem
    1. 5.1 Channel subsystem
      1. 5.1.1 Multiple logical channel subsystems
      2. 5.1.2 Multiple subchannel sets
      3. 5.1.3 Channel path spanning
    2. 5.2 I/O configuration management
    3. 5.3 Channel subsystem summary
  9. Chapter 6. Cryptographic features
    1. 6.1 Cryptography enhancements on IBM z15
    2. 6.2 Cryptography overview
      1. 6.2.1 Modern cryptography
      2. 6.2.2 Kerckhoffs’ principle
      3. 6.2.3 Keys
      4. 6.2.4 Algorithms
    3. 6.3 Cryptography on IBM z15
    4. 6.4 CP Assist for Cryptographic Functions
      1. 6.4.1 Cryptographic synchronous functions
      2. 6.4.2 CPACF protected key
    5. 6.5 Crypto Express7S
      1. 6.5.1 Cryptographic asynchronous functions
      2. 6.5.2 Crypto Express7S as a CCA coprocessor
      3. 6.5.3 Crypto Express7S as an EP11 coprocessor
      4. 6.5.4 Crypto Express7S as an accelerator
      5. 6.5.5 Managing Crypto Express7S
    6. 6.6 Trusted Key Entry workstation
      1. 6.6.1 Logical partition, TKE host, and TKE target
      2. 6.6.2 Optional smart card reader
      3. 6.6.3 TKE hardware support and migration information
    7. 6.7 Cryptographic functions comparison
    8. 6.8 Cryptographic operating system support for z15
      1. 6.8.1 Crypto Express7S Toleration
      2. 6.8.2 Crypto Express7S support of VFPE
      3. 6.8.3 Crypto Express7S support of greater than 16 domains
  10. Chapter 7. Operating system support
    1. 7.1 Operating systems summary
    2. 7.2 Support by operating system
      1. 7.2.1 z/OS
      2. 7.2.2 z/VM
      3. 7.2.3 z/VSE
      4. 7.2.4 z/TPF
      5. 7.2.5 Linux on IBM Z (Linux on Z)
      6. 7.2.6 KVM hypervisor
    3. 7.3 z15 features and function support overview
      1. 7.3.1 Supported CPC functions
      2. 7.3.2 Coupling and clustering
      3. 7.3.3 Network connectivity
      4. 7.3.4 Cryptographic functions
    4. 7.4 Support by features and functions
      1. 7.4.1 LPAR Configuration and Management
      2. 7.4.2 Base CPC features and functions
      3. 7.4.3 Coupling and clustering features and functions
      4. 7.4.4 Storage connectivity-related features and functions
      5. 7.4.5 Networking features and functions
      6. 7.4.6 Cryptography Features and Functions Support
    5. 7.5 z/OS migration considerations
      1. 7.5.1 General guidelines
      2. 7.5.2 Hardware Fix Categories (FIXCATs)
      3. 7.5.3 Coupling links
      4. 7.5.4 z/OS XL C/C++ considerations
      5. 7.5.5 z/OS V2.4
      6. 7.5.6 z/OS V2.3
    6. 7.6 z/VM migration considerations
      1. 7.6.1 z/VM 7.2
      2. 7.6.2 z/VM 7.1
      3. 7.6.3 z/VM V6.4
      4. 7.6.4 ESA/390-compatibility mode for guests
      5. 7.6.5 Capacity
    7. 7.7 z/VSE migration considerations
    8. 7.8 Software licensing
    9. 7.9 References
  11. Chapter 8. System upgrades
    1. 8.1 Permanent and Temporary Upgrades
      1. 8.1.1 Overview
      2. 8.1.2 CoD for z15 systems-related terminology
      3. 8.1.3 Concurrent and nondisruptive upgrades
      4. 8.1.4 Permanent upgrades
      5. 8.1.5 Temporary upgrades
    2. 8.2 Concurrent upgrades
      1. 8.2.1 PU Capacity feature upgrades
      2. 8.2.2 Customer Initiated Upgrade facility
      3. 8.2.3 Concurrent upgrade functions summary
    3. 8.3 Miscellaneous equipment specification upgrades
      1. 8.3.1 MES upgrade for processors
      2. 8.3.2 MES upgrades for memory
      3. 8.3.3 MES upgrades for I/O
      4. 8.3.4 Feature on Demand
      5. 8.3.5 Summary of plan-ahead feature
    4. 8.4 Permanent upgrade by using the CIU facility
      1. 8.4.1 Ordering
      2. 8.4.2 Retrieval and activation
    5. 8.5 On/Off Capacity on Demand
      1. 8.5.1 Overview
      2. 8.5.2 Capacity Provisioning Manager
      3. 8.5.3 Ordering
      4. 8.5.4 On/Off CoD testing
      5. 8.5.5 Activation and deactivation
      6. 8.5.6 Termination
    6. 8.6 z/OS Capacity Provisioning
    7. 8.7 System Recovery Boost Upgrade
    8. 8.8 Capacity for Planned Event
    9. 8.9 Capacity Backup
      1. 8.9.1 Ordering
      2. 8.9.2 CBU activation and deactivation
      3. 8.9.3 Automatic CBU enablement for GDPS
    10. 8.10 Planning for nondisruptive upgrades
      1. 8.10.1 Components
      2. 8.10.2 Concurrent upgrade considerations
    11. 8.11 Summary of Capacity on-Demand offerings
  12. Chapter 9. Reliability, availability, and serviceability
    1. 9.1 RAS strategy
    2. 9.2 Technology
      1. 9.2.1 Processor Unit chip
      2. 9.2.2 System Controller and main memory
      3. 9.2.3 I/O and service
    3. 9.3 Structure
    4. 9.4 Reducing complexity
    5. 9.5 Reducing touches
    6. 9.6 z15 availability characteristics
    7. 9.7 z15 RAS functions
      1. 9.7.1 Scheduled outages
      2. 9.7.2 Unscheduled outages
    8. 9.8 z15 enhanced drawer availability
      1. 9.8.1 EDA planning considerations
      2. 9.8.2 Enhanced drawer availability processing
    9. 9.9 z15 Enhanced Driver Maintenance
      1. 9.9.1 Resource Group and native PCIe features MCLs
    10. 9.10 RAS capability for the HMC and SE
  13. Chapter 10. Hardware Management Console and Support Element
    1. 10.1 HMC and SE introduction
      1. 10.1.1 Dynamic Partition Manager support
    2. 10.2 HMC and SE changes and new features
      1. 10.2.1 Driver Level 41 HMC and SE new features
      2. 10.2.2 New Rack-mounted HMC and Tower HMC
      3. 10.2.3 New Support Element
      4. 10.2.4 New service and functional operations for HMCs and SEs
      5. 10.2.5 SE driver support with the HMC driver
      6. 10.2.6 HMC feature codes
      7. 10.2.7 User interface
      8. 10.2.8 Customize Product Engineering Access: Best practice
    3. 10.3 HMC and SE connectivity
      1. 10.3.1 Standard HMC connectivity
      2. 10.3.2 Hardware Management Appliance
      3. 10.3.3 Network planning for the HMC and SE
      4. 10.3.4 Hardware considerations
      5. 10.3.5 TCP/IP Version 6 on the HMC and SE
      6. 10.3.6 OSA Support Facility
      7. 10.3.7 Assigning addresses to the HMC and SE
      8. 10.3.8 HMC Multi-factor authentication
    4. 10.4 Remote Support Facility
      1. 10.4.1 Security characteristics
      2. 10.4.2 RSF connections to IBM and Enhanced IBM Service Support System
      3. 10.4.3 HMC and SE remote operations
    5. 10.5 HMC and SE capabilities
      1. 10.5.1 Central processor complex management
      2. 10.5.2 LPAR management
      3. 10.5.3 Operating system communication
      4. 10.5.4 HMC and SE microcode
      5. 10.5.5 Monitoring
      6. 10.5.6 Capacity on-demand support
      7. 10.5.7 Server Time Protocol support
      8. 10.5.8 CTN Split and Merge
      9. 10.5.9 NTP client and server support on the HMC
      10. 10.5.10 Security and user ID management
      11. 10.5.11 System Input/Output Configuration Analyzer on the SE and HMC
      12. 10.5.12 Automated operations
      13. 10.5.13 Cryptographic support
      14. 10.5.14 Installation support for z/VM that uses the HMC
      15. 10.5.15 Dynamic Partition Manager
  14. Chapter 11. Environmentals
    1. 11.1 Power and Cooling
      1. 11.1.1 Intelligent Power Distribution Unit (iPDU)
      2. 11.1.2 Bulk Power assembly (BPA)
      3. 11.1.3 Cooling requirements
      4. 11.1.4 Internal Battery Feature
    2. 11.2 Physical specifications
    3. 11.3 Physical planning
      1. 11.3.1 Raised floor or non-raised floor
      2. 11.3.2 Top Exit cabling feature (optional)
      3. 11.3.3 Top or bottom exit cables
      4. 11.3.4 Bottom Exit cabling feature
      5. 11.3.5 Frame Bolt-down kit
      6. 11.3.6 Service clearance areas
    4. 11.4 Energy management
      1. 11.4.1 Environmental monitoring
  15. Chapter 12. Performance
    1. 12.1 IBM z15 performance characteristics
      1. 12.1.1 z15 single-thread capacity
      2. 12.1.2 z15 SMT capacity
      3. 12.1.3 IBM Integrated Accelerator for zEnterprise Data Compression
      4. 12.1.4 Primary performance improvement drivers with z15
    2. 12.2 z15 Large System Performance Reference ratio
      1. 12.2.1 LSPR workload suite
    3. 12.3 Fundamental components of workload performance
      1. 12.3.1 Instruction path length
      2. 12.3.2 Instruction complexity
      3. 12.3.3 Memory hierarchy and memory nest
    4. 12.4 Relative Nest Intensity
    5. 12.5 LSPR workload categories based on RNI
    6. 12.6 Relating production workloads to LSPR workloads
    7. 12.7 CPU MF counter data and LSPR workload type
    8. 12.8 Workload performance variation
    9. 12.9 Capacity planning consideration for z15
      1. 12.9.1 Collect CPU MF counter data
      2. 12.9.2 Creating EDF file with CP3KEXTR
      3. 12.9.3 Loading EDF file to the capacity planning tool
      4. 12.9.4 Tips to maximize z15 server capacity
  16. Appendix A. Channel options
  17. Appendix B. System Recovery Boost
    1. B.1 Overview
    2. B.2 Functions
    3. B.3 Delivering extra capacity
    4. B.4 Setting up the System Recovery Boost
    5. B.5 Monitoring System Recovery Boost
    6. B.6 Automation
    7. B.7 Pricing
    8. B.8 Software support
  18. Appendix C. IBM Integrated Accelerator for zEnterprise Data Compression
    1. Client value of Z compression
    2. z15 IBM Integrated Accelerator for zEDC
    3. z15 migration considerations
    4. Software support
    5. Compression acceleration and Linux on Z
  19. Appendix D. Frame configurations
    1. Power Distribution Unit configurations
    2. Bulk Power Assembly configurations
  20. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. Help from IBM
  21. Back cover

Product information

  • Title: IBM z15 (8561) Technical Guide
  • Author(s): Octavian Lascu, John Troy, Jannie Houlbjerg, Frank Packheiser, Paul Schouten, Kazuhiro Nakajima, Anna Shugol, Hervey Kamga, Bo XU
  • Release date: May 2024
  • Publisher(s): IBM Redbooks
  • ISBN: 9780738458120