Chapter 4. IBM System x3690 X5 131
the parallelization of workloads. When Hyper-Threading is engaged in the BIOS, for each
processor core that is physically present, the operating system addresses two. For more
information, see 2.2.2, “Hyper-Threading Technology” on page 17.
All CPU options include a heat-sink.
The x3690 X5 models include one CPU standard. All five PCIe slots are usable, even with
only one processor installed, as shown in Figure 4-8 on page 126.
The second CPU is required to access the memory in the memory mezzanine (if the memory
mezzanine is installed). The second CPU can be installed without the memory mezzanine,
but its only access to memory is through the primary CPU. For optimal performance, if two
CPUs are installed, install a memory mezzanine also.
Follow these population guidelines:
Each CPU requires a minimum of two DIMMs to operate. If the memory mezzanine is
installed, it needs a minimum of two DIMMs installed.
Both processors must be identical.
Consider the X7542 processor for CPU frequency-dependent workloads, because it has
the highest core frequency of the available processor models.
The MAX5 is supported with either one or two processors installed in the x3690 X5,
although the recommendation is to have two processors installed and memory installed in
every DIMM socket in the server to maximize performance.
If high processing capacity is not required for your application but high memory bandwidth
is required, consider using two processors with fewer cores or a lower core frequency
rather than two processors with more cores or a higher core frequency. Having four
processors can enable all memory channels and can maximize memory bandwidth. We
describe this technique in 4.8, “Memory” on page 131.
4.8 Memory
The x3690 X5 offers up to 32 DIMM sockets that are internal to the server chassis, plus an
additional 32 DIMM sockets in the MAX5 memory expansion unit.
This section covers the following topics:
4.8.1, “Memory DIMM options” on page 133
4.8.2, “x3690 X5 memory population order” on page 133
4.8.3, “MAX5 memory” on page 136
4.8.4, “Memory balance” on page 139
4.8.5, “Mixing DIMMs and the performance effect” on page 140
4.8.6, “Memory mirroring” on page 141
4.8.7, “Memory sparing” on page 143
4.8.8, “Effect on performance of using mirroring or sparing” on page 144
Implement the memory DIMMs that are internal to the x3690 X5 chassis:
16 DIMM sockets on the system planar
16 DIMM sockets in an optional memory mezzanine
Tip: The memory mezzanine is referred to in the announcement letter as the memory
expansion card
. It is referred to as the memory tray, in the Installation and User’s Guide
- IBM System x3690 X5.
132 IBM eX5 Implementation Guide
The memory mezzanine is an optional component and orderable as listed in Table 4-6.
Table 4-6 x3690 X5 memory mezzanine option part number
Figure 4-13 shows the memory mezzanine and DIMMs.
Figure 4-13 Location of the memory DIMMs
With the Intel Xeon 6500 and 7500 processors, the memory controller is integrated into the
processor, as shown in the architecture block diagram in Figure 4-8 on page 126:
Processor 0 connects directly to the memory buffers and memory DIMM sockets on the
system planar.
Processor 1 connects directly to the memory buffers and memory in the memory
mezzanine.
If you plan to install the memory mezzanine, you are required to also install the second
processor.
The x3690 X5 uses the Intel scalable memory buffer to provide DDR3 SDRAM memory
functions. The memory buffers connect to the memory controller in each processor through
Intel Scalable Memory Interconnect links. Each memory buffer has two memory channels,
and the DIMM sockets are connected to the memory buffer with two DIMMs per memory
channel (2 DPC).
Option Feature code Description
60Y0323 9278 IBM x3690 X5 16-DIMM Internal Memory Expansion
Memory
mezzanine
Memory
mezzanine
Installing the
memory mezzanine
into the server
Memory DIMMs on the
system board
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