IBM eServer zSeries 990 Technical Guide

IBM eServer zSeries 990 Technical Guide

by Bill White, Mario Almeida, Dick Jorna
Released May 2004
Publisher(s): IBM Redbooks
ISBN: None

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Book description

The IBM Eserver zSeries® 990 scalable server provides major extensions to the existing zSeries architecture and capabilities. The concept of Logical Channel Subsystems is added, and the maximum number of Processor Units and logical partitions is increased. These extensions provide the base for much larger zSeries servers.

This IBM® IBM Redbooks publication is intended for IBM systems engineers, consultants, and customers who need to understand the zSeries 990 features, functions, availability, and services.
This publication is part of a series. For a complete understanding of the z990 scalable server capabilities, also refer to our companion Redbooks:

IBM Eserver zSeries 990 Technical Introduction, SG24-6863
IBM Eserver zSeries Connectivity Handbook, SG24-5444

Note that the information in this book includes features and functions announced on April 7, 2004, and that certain functionality is not available until hardware Driver Level 55 is installed on the z990 server.

Table of contents

  1. Notices
    1. Trademarks
  2. Preface
    1. The team that wrote this redbook
    2. Become a published author
    3. Comments welcome
  3. Chapter 1: zSeries 990 overview
    1. Introduction
    2. z990 models
    3. System functions and features
      1. Processor
      2. Memory
      3. Self-Timed Interconnect (STI)
      4. Channel Subsystem (CSS)
      5. Physical Channel IDs (PCHIDs) and CHPID Mapping Tool
      6. Spanned channels
      7. I/O connectivity
      8. Cryptographic
      9. Parallel Sysplex support
      10. Intelligent Resource Director (IRD)
      11. Hardware consoles
      12. Concurrent upgrades
      13. Performance
      14. Reliability, Availability, and Serviceability (RAS)
      15. Software
      16. Software support
      17. Summary
  4. Chapter 2: System structure and design
    1. System structure
      1. Book concept
      2. Models
      3. Memory
      4. Ring topology
      5. Connectivity
      6. Frames and cages
      7. The MCM
      8. The PU, SC, and SD chips
      9. Summary
    2. System design
      1. Design highlights
      2. Book design
      3. Processor Unit design
      4. Processor Unit functions (1/2)
      5. Processor Unit functions (2/2)
      6. Memory design
      7. Modes of operation (1/2)
      8. Modes of operation (2/2)
      9. Model configurations
      10. Storage operations
      11. Reserved storage
      12. LPAR storage granularity
      13. LPAR Dynamic Storage Reconfiguration (DSR)
      14. I/O subsystem
      15. Channel Subsystem
  5. Chapter 3: I/O system structure
    1. Overview
    2. I/O cages
      1. Self-Timed Interconnect (STI)
      2. STIs and I/O cage connections
      3. Balancing I/O connections
    3. I/O and cryptographic feature cards
      1. I/O feature cards
      2. Cryptographic feature cards
      3. Physical Channel IDs (PCHIDs)
    4. Connectivity
      1. I/O and cryptographic features support and configuration rules
      2. ESCON channel
      3. FICON channel
      4. OSA-Express adapter
      5. Coupling Facility links
      6. External Time Reference (ETR) feature
      7. Cryptographic features
  6. Chapter 4: Channel Subsystem
    1. Multiple Logical Channel Subsystem (LCSS)
      1. Logical Channel Subsystem structure
      2. Physical Channel ID (PCHID)
      3. Channel spanning
    2. LCSS configuration management
      1. z990 configuration management
    3. LCSS-related numbers
  7. Chapter 5: Cryptography
    1. Cryptographic function support
      1. Cryptographic Synchronous functions
      2. Cryptographic Asynchronous functions
    2. z990 Cryptographic processors
      1. CP Assist for Cryptographic Function (CPACF)
      2. PCIX Cryptographic Coprocessor (PCIXCC)
      3. PCI Cryptographic Accelerator (PCICA) feature
    3. Cryptographic hardware features
      1. PCIX Cryptographic Coprocessor feature
      2. The PCICA feature
      3. Configuration rules
      4. z990 cryptographic feature codes
      5. TKE workstation feature
    4. Cryptographic features comparison
    5. Software requirements
  8. Chapter 6: Software support
    1. Operating system support
    2. z/OS software support
      1. Compatibility Support for z/OS
      2. Exploitation Support for z/OS
      3. HCD support
      4. Automation changes
      5. SMF support
      6. RMF support
      7. ICKDSF requirements
      8. ICSF support
      9. Additional Exploitation Support considerations
    3. z/VM software support
    4. z/VSE and VSE/ESA software support
    5. TPF software support
    6. Linux software support
    7. Summary of software requirements
      1. Summary of z/OS and OS/390 software requirements
      2. Summary of z/VM, z/VSE, VSE/ESA, TPF, and Linux software requirements
    8. Workload License Charges
    9. Concurrent upgrades considerations
  9. Chapter 7: Sysplex functions
    1. Parallel Sysplex
      1. Parallel Sysplex described
      2. Parallel Sysplex summary
    2. Sysplex and Coupling Facility considerations
      1. Sysplex configurations and Sysplex Timer considerations
      2. Coupling Facility and CFCC considerations
      3. CFCC enhanced patch apply
      4. Coupling Facility link connectivity
      5. Coupling Facility Resource Manager (CFRM) policy considerations
      6. ICF processor assignments
      7. Dynamic CF dispatching and dynamic ICF expansion
    3. System-managed CF structure duplexing
      1. Benefits
      2. CF structure duplexing
      3. Configuration planning
    4. Geographically Dispersed Parallel Sysplex
      1. GDPS/PPRC
      2. GDPS/XRC
      3. GDPS and Capacity Backup (CBU)
    5. Intelligent Resource Director
      1. LPAR CPU management
      2. Dynamic Channel Path Management
      3. Channel Subsystem Priority Queueing
      4. WLM and Channel Subsystem priority
      5. Special considerations and restrictions
      6. References
  10. Chapter 8: Capacity upgrades
    1. Concurrent upgrades
    2. Capacity Upgrade on Demand (CUoD) (1/2)
    3. Capacity Upgrade on Demand (CUoD) (2/2)
    4. Customer Initiated Upgrade (CIU) (1/2)
    5. Customer Initiated Upgrade (CIU) (2/2)
    6. On/Off Capacity on Demand (On/Off CoD)
    7. Capacity BackUp (CBU)
    8. Nondisruptive upgrades
      1. Upgrade scenarios (1/2)
      2. Upgrade scenarios (2/2)
      3. Planning for nondisruptive upgrades
    9. Capacity planning considerations
      1. Balanced system design
      2. Superscalar processors
      3. Integrated hardware and system assists
    10. Capacity measurements
      1. Large Systems Performance Reference (LSPR) (1/2)
      2. Large Systems Performance Reference (LSPR) (2/2)
  11. Chapter 9: Environmental requirements
    1. Introduction
      1. Power and cooling requirements
      2. Power consumption
      3. Internal Battery Feature
      4. Emergency power-off
      5. Cooling requirements
    2. Weights
    3. Dimensions
  12. Appendix A: Hardware Management Console (HMC)
    1. z990 Hardware Management Console
      1. Token ring only wiring scenario
      2. Ethernet only - one-path wiring scenario
      3. Ethernet only - two-path wiring scenario
      4. Token ring and Ethernet wiring scenario
      5. Remote operations
      6. Support Element
      7. z990 HMC enhancements
  13. Appendix B: Fiber optic cabling services
    1. Fiber optic cabling services from IBM
    2. Summary
  14. Glossary (1/2)
  15. Glossary (2/2)
  16. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. How to get IBM Redbooks
  17. Index (1/2)
  18. Index (2/2)
  19. Back cover

Product information

  • Title: IBM eServer zSeries 990 Technical Guide
  • Author(s): Bill White, Mario Almeida, Dick Jorna
  • Release date: May 2004
  • Publisher(s): IBM Redbooks
  • ISBN: None