Dramatic increases in processing power, fueled by a combination of integrated circuit scaling and shifts in computer architectures from single-core to future many-core systems, has rapidly scaled on-chip aggregate bandwidths into the Tb/s range, necessitating a corresponding increase in the amount of data communicated between chips to not limit overall system performance. The two conventional methods to increase interchip communication bandwidth include raising both the per-channel data rate and the I/O number. This book discusses these challenges associated with scaling I/O data rates and current design techniques. It describes the major highspeed components, channel properties, and performance metrics.
Increasing interchip communication ...
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