Future Trends in Microelectronics: From Nanophotonics to Sensors to Energy

Simulation of Self-Heating Effects in Different SOI MOS Architectures

Enrico Sangiorgi, Marco Braccioli, and Claudio Fiegna

ARCES-DEIS University of Bologna and IUNET Via Venezia 260, 47521 Cesena, Italy

1.   Introduction

The demand for high circuit performance has been addressed historically by miniaturization of device dimensions and increased device packing densities.^1,2

The International Technology Roadmap of Semiconductors (ITRS)³ imposes aggressive scaling trends for the gate length (L_G) and equivalent gate oxide thickness (EOT) to achieve a 17% annual reduction of the intrinsic switching delay (CV/I) for high-performance transistors. Over time, this strategy has become insufficient because of mobility degradation due to the increasing channel-doping density. Furthermore, it has become increasingly difficult to control undesirable phenomena, such as leakage current across the gate oxide, short-channel effects causing an excessive I_OFF current (the subthreshold current in a transistor that is nominally off), a large dependence of threshold voltage V_T on drain bias, and the variability of V_T due to statistical fluctuations of physical parameters like channel length and the number of dopant atoms in the channel.⁴

Technology scaling also impacts power dissipation. The classic constant-field scaling rule predicts a significant reduction of the dynamic power in a given circuit, proportional to fCV_DD², whereas the power dissipation per unit area is expected to stay constant. Actual ...