Future Trends in Microelectronics: Up the Nano Creek

MRAM Downscaling Challenges

F. Arnaud d’Avitaya and V. Safarov

CRMCN−CNRS, Campus de Luminy, 13288 Marseille cedex 9, France

A. Filipe

Spintron, Technopôle de Château-Gombert – BP100, 13382 Marseille, France

1.   Introduction

Memoriesⁱ play a major role in achieving superior computer performance. Indeed, the execution rate of a code is not only related to the processor clocking, but greatly depends on the writing and reading rate of the data to and from memory. Aside from the large hard-disk memories, which now reach capacities and performance unimaginable only ten years ago, the memory chips presently used in computer cores can be classified in different ways depending on the data retention mode and the technology used, but they essentially rest on two concepts: i) the core of the device is essentially based on MOS transistors, and ii) there is random access to the data (hence the acronym RAM, for random access memory).

Within the RAM family, we can distinguish two main classes: the dynamic RAM (DRAM) that has a simple single-transistor architecture but needs to be refreshed regularly (because reading erases the data stored in a capacitor), and static RAM (SRAM) that need not be refreshed but requires a more complex architecture detrimental to the integration density. Despite the fact that they are extremely fast and therefore well-adapted to the computer’s requirements, both these technologies suffer from a major drawback: memory is erased when the power is switched off. This ...