Engineering Digital Design

Engineering Digital Design

by Richard F. Tinder
Released January 2000
Publisher(s): Academic Press
ISBN: 9780080505657

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Book description

Engineering Digital Design, Second Edition provides the most extensive coverage of any available textbook in digital logic and design. The new REVISED Second Edition published in September of 2002 provides 5 productivity tools free on the accompanying CD ROM. This software is also included on the Instructor's Manual CD ROM and complete instructions accompany each software program.

In the REVISED Second Edition modern notation combines with state-of-the-art treatment of the most important subjects in digital design to provide the student with the background needed to enter industry or graduate study at a competitive level. Combinatorial logic design and synchronous and asynchronous sequential machine design methods are given equal weight, and new ideas and design approaches are explored.

The productivity tools provided on the accompanying CD are outlined below:
[1] EXL-Sim2002 logic simulator: EXL-Sim2002 is a full-featured, interactive, schematic-capture and simulation program that is ideally suited for use with the text at either the entry or advanced-level of logic design. Its many features include drag-and-drop capability, rubber banding, mixed logic and positive logic simulations, macro generation, individual and global (or randomized) delay assignments, connection features that eliminate the need for wire connections, schematic page sizing and zooming, waveform zooming and scrolling, a variety of printout capabilities, and a host of other useful features.

[2] BOOZER logic minimizer: BOOZER is a software minimization tool that is recommended for use with the text. It accepts entered variable (EV) or canonical (1's and 0's) data from K-maps or truth tables, with or without don't cares, and returns an optimal or near optimal single or multi-output solution. It can handle up to 12 functions Boolean functions and as many inputs when used on modern computers.

[3] ESPRESSO II logic minimizer: ESPRESSO II is another software minimization tool widely used in schools and industry. It supports advanced heuristic algorithms for minimization of two-level, multi-output Boolean functions but does not accept entered variables. It is also readily available from the University of California, Berkeley, 1986 VLSI Tools Distribution.

[4] ADAM design software: ADAM (for Automated Design of Asynchronous Machines) is a very powerful productivity tool that permits the automated design of very complex asynchronous state machines, all free of timing defects. The input files are state tables for the desired state machines. The output files are given in the Berkeley format appropriate for directly programming PLAs. ADAM also allows the designer to design synchronous state machines, timing-defect-free. The options include the lumped path delay (LPD) model or NESTED CELL model for asynchronous FSM designs, and the use of D FLIP-FLOPs for synchronous FSM designs. The background for the use of ADAM is covered in Chapters 11, 14 and 16 of the REVISED 2nd Edition.

[5] A-OPS design software: A-OPS (for Asynchronous One-hot Programmable Sequencers) is another very powerful productivity tool that permits the design of asynchronous and synchronous state machines by using a programmable sequencer kernel. This software generates a PLA or PAL output file (in Berkeley format) or the VHDL code for the automated timing-defect-free designs of the following: (a) Any 1-Hot programmable sequencer up to 10 states. (b) The 1-Hot design of multiple asynchronous or synchronous state machines driven by either PLDs or RAM. The input file is that of a state table for the desired state machine. This software can be used to design systems with the capability of instantly switching between several radically different controllers on a
time-shared basis. The background for the use of A-OPS is covered in Chapters 13, 14 and 16 of the REVISED 2nd Edition.

Table of contents

  1. Cover (1/2)
  2. Cover (2/2)
  3. Contents (1/2)
  4. Contents (2/2)
  5. Preface (1/2)
  6. Preface (2/2)
  7. Chapter 1. Introductory Remarks and Glossary
    1. 1.1 What Is So Special about Digital Systems?
    2. 1.2 The Year 2000 and Beyond?
    3. 1.3 A Word of Warning
    4. 1.4 Glossary of Terms, Expressions, and Abbreviations
  8. Chapter 2. Number Systems, Binary Arithmetic, and Codes
    1. 2.1 Introduction
    2. 2.2 Positional and Polynomial Representations
    3. 2.3 Unsigned Binary Number System
    4. 2.4 Unsigned Binary Coded Decimal, Hexadecimal, and Octal
    5. 2.5 Conversion between Number Systems (1/2)
    6. 2.5 Conversion between Number Systems (2/2)
    7. 2.6 Signed Binary Numbers (1/2)
    8. 2.6 Signed Binary Numbers (2/2)
    9. 2.7 Excess (Offset) Representations
    10. 2.8 Floating-Point Number Systems
    11. 2.9 Binary Arithmetic (1/4)
    12. 2.9 Binary Arithmetic (2/4)
    13. 2.9 Binary Arithmetic (3/4)
    14. 2.9 Binary Arithmetic (4/4)
    15. 2.10 Other Codes
    16. Further Reading
    17. Problems
  9. Chapter 3. Background for Digital Design
    1. 3.1 Introduction
    2. 3.2 Binary State Terminology and Mixed Logic Notation
    3. 3.3 Introduction to CMOS Terminology and Symbology
    4. 3.4 Logic Level Conversion: The Inverter
    5. 3.5 Transmission Gates and Tri-State Drivers
    6. 3.6 AND and OR Operators and Their Mixed-Logic Circuit Symbology (1/2)
    7. 3.6 AND and OR Operators and Their Mixed-Logic Circuit Symbology (2/2)
    8. 3.7 Logic Level Incompatibility: Complementation
    9. 3.8 Reading and Construction of Mixed-Logic Circuits
    10. 3.9 XOR and EQV Operators and Their Mixed-Logic Circuit Symbology (1/2)
    11. 3.9 XOR and EQV Operators and Their Mixed-Logic Circuit Symbology (2/2)
    12. 3.10 Laws of Boolean Algebra (1/2)
    13. 3.10 Laws of Boolean Algebra (2/2)
    14. 3.11 Laws of XOR Algebra
    15. 3.12 Worked Examples
    16. Further Reading
    17. Problems (1/2)
    18. Problems (2/2)
  10. Chapter 4. Logic Function Representation and Minimization
    1. 4.1 Introduction
    2. 4.2 SOP and POS Forms
    3. 4.3 Introduction to Logic Function Graphics (1/2)
    4. 4.3 Introduction to Logic Function Graphics (2/2)
    5. 4.4 Karnaugh Map Function Minimization (1/2)
    6. 4.4 Karnaugh Map Function Minimization (2/2)
    7. 4.5 Multiple Output Optimization (1/2)
    8. 4.5 Multiple Output Optimization (2/2)
    9. 4.6 Entered Variable K-map Minimization (1/2)
    10. 4.6 Entered Variable K-map Minimization (2/2)
    11. 4.7 Function Reduction of Five or More Variables
    12. 4.8 Minimization Algorithms and Application
    13. 4.9 Factorization, Resubstitution, and Decomposition Methods (1/2)
    14. 4.9 Factorization, Resubstitution, and Decomposition Methods (2/2)
    15. 4.10 Design Area vs Performance
    16. 4.11 Perspective on Logic Minimization and Optimization
    17. 4.12 Worked EV K-map Examples
    18. Further Reading
    19. Problems (1/2)
    20. Problems (2/2)
  11. Chapter 5. Function Minimization by Using K-map XOR Patterns and Reed–Muller Transformation Forms
    1. 5.1 Introduction
    2. 5.2 XOR-Type Patterns and Extraction of Gate-Minimum Cover from EV K-maps (1/2)
    3. 5.2 XOR-Type Patterns and Extraction of Gate-Minimum Cover from EV K-maps (2/2)
    4. 5.3 Algebraic Verification of Optimal XOR Function Extraction from K-maps
    5. 5.4 K-map Plotting and Entered Variable XOR Patterns
    6. 5.5 The SOP-to-EXSOP Reed–Muller Transformation
    7. 5.6 The POS-to-EQPOS Reed–Muller Transformation
    8. 5.7 Examples of Minimum Function Extraction (1/2)
    9. 5.7 Examples of Minimum Function Extraction (2/2)
    10. 5.8 Heuristics for CRMT Minimization
    11. 5.9 Incompletely Specified Functions
    12. 5.10 Multiple Output Functions with Don’t Cares
    13. 5.11 K-map Subfunction Partitioning for Combined CRMT and Two-Level Minimization
    14. 5.12 Perspective on the CRMT and CRMT/Two-Level Minimization Methods
    15. Further Reading
    16. Problems (1/2)
    17. Problems (2/2)
  12. Chapter 6. Nonarithmetic Combinational Logic Devices
    1. 6.1 Introduction and Background
    2. 6.2 Multiplexers (1/2)
    3. 6.2 Multiplexers (2/2)
    4. 6.3 Decoders/Demultiplexers (1/2)
    5. 6.3 Decoders/Demultiplexers (2/2)
    6. 6.4 Encoders
    7. 6.5 Code Converters (1/2)
    8. 6.5 Code Converters (2/2)
    9. 6.6 Magnitude Comparators (1/2)
    10. 6.6 Magnitude Comparators (2/2)
    11. 6.7 Parity Generators and Error Checking Systems
    12. 6.8 Combinational Shifters
    13. 6.9 Steering Logic and Tri-State Gate Applications
    14. 6.10 Introduction to VHDL Description of Combinational Primitives (1/2)
    15. 6.10 Introduction to VHDL Description of Combinational Primitives (2/2)
    16. Further Reading
    17. Problems (1/2)
    18. Problems (2/2)
  13. Chapter 7. Programmable Logic Devices
    1. 7.1 Introduction
    2. 7.2 Read-Only Memories
    3. 7.3 Programmable Logic Arrays (1/2)
    4. 7.3 Programmable Logic Arrays (2/2)
    5. 7.4 Programmable Array Logic Devices
    6. 7.5 Mixed-Logic Inputs to and Outputs from ROMs, PLAs, and PAL Devices
    7. 7.6 Multiple PLD Schemes for Augmenting Input and Output Capability
    8. 7.7 Introduction to FPGAs and Other General-Purpose Devices (1/3)
    9. 7.7 Introduction to FPGAs and Other General-Purpose Devices (2/3)
    10. 7.7 Introduction to FPGAs and Other General-Purpose Devices (3/3)
    11. 7.8 CAD Help in Programming PLD Devices
    12. Further Reading
    13. Problems
  14. Chapter 8. Arithmetic Devices and Arithmetic Logic Units (ALUs)
    1. 8.1 Introduction
    2. 8.2 Binary Adders
    3. 8.3 Binary Subtractors
    4. 8.4 The Carry Look-Ahead Adder
    5. 8.5 Multiple-Number Addition and the Carry-Save Adder
    6. 8.6 Multipliers
    7. 8.7 Parallel Dividers
    8. 8.8 Arithmetic and Logic Units (1/3)
    9. 8.8 Arithmetic and Logic Units (2/3)
    10. 8.8 Arithmetic and Logic Units (3/3)
    11. 8.9 Dual-Rail Systems and ALUs with Completion Signals (1/3)
    12. 8.9 Dual-Rail Systems and ALUs with Completion Signals (2/3)
    13. 8.9 Dual-Rail Systems and ALUs with Completion Signals (3/3)
    14. 8.10 VHDL Description of Arithmetic Devices
    15. Further Reading
    16. Problems (1/2)
    17. Problems (2/2)
  15. Chapter 9. Propagation Delay and Timing Defects in Combinational Logic
    1. 9.1 Introduction
    2. 9.2 Static Hazards in Two-Level Combinational Logic Circuits (1/2)
    3. 9.2 Static Hazards in Two-Level Combinational Logic Circuits (2/2)
    4. 9.3 Detection and Elimination Hazards in Multilevel XOR-Type Functions (1/3)
    5. 9.3 Detection and Elimination Hazards in Multilevel XOR-Type Functions (2/3)
    6. 9.3 Detection and Elimination Hazards in Multilevel XOR-Type Functions (3/3)
    7. 9.4 Function Hazards
    8. 9.5 Stuck-at Faults and the Effect of Hazard Cover on Fault Testability
    9. Further Reading
    10. Problems
  16. Chapter 10. Introduction to Synchronous State Machine Design and Analysis
    1. 10.1 Introduction
    2. 10.2 Models for Sequential Machines
    3. 10.3 The Fully Documented State Diagram: The Sum Rule
    4. 10.4 The Basic Memory Cells (1/2)
    5. 10.4 The Basic Memory Cells (2/2)
    6. 10.5 Introduction to Flip-Flops
    7. 10.6 Procedure for FSM (Flip-Flop) Design and the Mapping Algorithm
    8. 10.7 The D Flip-Flops: General (1/2)
    9. 10.7 The D Flip-Flops: General (2/2)
    10. 10.8 Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops (1/3)
    11. 10.8 Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops (2/3)
    12. 10.8 Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops (3/3)
    13. 10.9 Latches and Flip-Flops with Serious Timing Problems: A Warning
    14. 10.10 Asynchronous Preset and Clear Overrides
    15. 10.11 Setup and Hold-Time Requirements of Flip-Flops
    16. 10.12 Design of Simple Synchronous State Machines with Edge-Triggered Flip- Flops: Map Conversion (1/2)
    17. 10.12 Design of Simple Synchronous State Machines with Edge-Triggered Flip- Flops: Map Conversion (2/2)
    18. 10.13 Analysis of Simple State Machines
    19. 10.14 VHDL Description of Simple State Machines
    20. Further Reading
    21. Problems (1/2)
    22. Problems (2/2)
  17. Chapter 11. Synchronous FSM Design Considerations and Applications
    1. 11.1 Introduction
    2. 11.2 Detection and Elimination of Output Race Glitches
    3. 11.3 Detection and Elimination of Static Hazards in the Output Logic (1/3)
    4. 11.3 Detection and Elimination of Static Hazards in the Output Logic (2/3)
    5. 11.3 Detection and Elimination of Static Hazards in the Output Logic (3/3)
    6. 11.4 Asynchronous Inputs: Rules and Caveats (1/2)
    7. 11.4 Asynchronous Inputs: Rules and Caveats (2/2)
    8. 11.5 Clock Skew
    9. 11.6 Clock Sources and Clock Signal Specifications
    10. 11.7 Initialization and Reset of the FSM: Sanity Circuits
    11. 11.8 Switch Debouncing Circuits
    12. 11.9 Applications to the Design of More Complex State Machines (1/2)
    13. 11.9 Applications to the Design of More Complex State Machines (2/2)
    14. 11.10 Algorithmic State Machine Charts and State Tables (1/2)
    15. 11.10 Algorithmic State Machine Charts and State Tables (2/2)
    16. 11.11 Array Algebraic Approach to Logic Design
    17. 11.12 State Minimization
    18. Further Reading
    19. Problems (1/2)
    20. Problems (2/2)
  18. Chapter 12. Module and Bit-Slice Devices
    1. 12.1 Introduction
    2. 12.2 Registers
    3. 12.3 Synchronous Binary Counters (1/4)
    4. 12.3 Synchronous Binary Counters (2/4)
    5. 12.3 Synchronous Binary Counters (3/4)
    6. 12.3 Synchronous Binary Counters (4/4)
    7. 12.4 Shift-Register Counters (1/2)
    8. 12.4 Shift-Register Counters (2/2)
    9. 12.5 Asynchronous (Ripple) Counters
    10. Further Reading
    11. Problems (1/2)
    12. Problems (2/2)
  19. Chapter 13. Alternative Synchronous FSM Architectures and Systems-Level Design
    1. 13.1 Introduction
    2. 13.2 Architecture Centered around Nonregistered PLDs (1/3)
    3. 13.2 Architecture Centered around Nonregistered PLDs (2/3)
    4. 13.2 Architecture Centered around Nonregistered PLDs (3/3)
    5. 13.3 State Machine Designs Centered around a Shift Register (1/2)
    6. 13.3 State Machine Designs Centered around a Shift Register (2/2)
    7. 13.4 State Machine Designs Centered around a Parallel Loadable Up/Down Counter
    8. 13.5 The One-Hot Design Method (1/3)
    9. 13.5 The One-Hot Design Method (2/3)
    10. 13.5 The One-Hot Design Method (3/3)
    11. 13.6 System-Level Design: Controller, Data Path, and Functional Partition (1/4)
    12. 13.6 System-Level Design: Controller, Data Path, and Functional Partition (2/4)
    13. 13.6 System-Level Design: Controller, Data Path, and Functional Partition (3/4)
    14. 13.6 System-Level Design: Controller, Data Path, and Functional Partition (4/4)
    15. 13.7 Dealing with Unusually Large Controller and System-Level Designs
    16. Further Reading
    17. Problems (1/3)
    18. Problems (2/3)
    19. Problems (3/3)
  20. Chapter 14. Asynchronous State Machine Design and Analysis: Basic Concepts
    1. 14.1 Introduction
    2. 14.2 The Lumped Path Delay Models for Asynchronous FSMs
    3. 14.3 Functional Relationships and the Stability Criteria
    4. 14.4 The Excitation Table for the LPD Model
    5. 14.5 State Diagrams, K-maps, and State Tables for Asynchronous FSMs
    6. 14.6 Design of the Basic Cells by Using the LPD Model
    7. 14.7 Design of the Rendezvous Modules by Using the Nested Cell Model
    8. 14.8 Design of the RET D Flip-Flop by Using the LPD Model
    9. 14.9 Design of the RET JK Flip-Flop by Flip-Flop Conversion
    10. 14.10 Detection and Elimination of Timing Defects in Asynchronous FSMs (1/4)
    11. 14.10 Detection and Elimination of Timing Defects in Asynchronous FSMs (2/4)
    12. 14.10 Detection and Elimination of Timing Defects in Asynchronous FSMs (3/4)
    13. 14.10 Detection and Elimination of Timing Defects in Asynchronous FSMs (4/4)
    14. 14.11 Initialization and Reset of Asynchronous FSMs
    15. 14.12 Single-Transition-Time Machines and the Array Algebraic Approach (1/2)
    16. 14.12 Single-Transition-Time Machines and the Array Algebraic Approach (2/2)
    17. 14.13 Hazard-Free Design of Fundamental Mode State Machines by Using the Nested Cell Approach
    18. 14.14 One-Hot Design of Asynchronous State Machines
    19. 14.15 Perspective on State Code Assignments of Fundamental Mode FSMs
    20. 14.16 Design of Fundamental Mode FSMs by Using PLDs
    21. 14.17 Analysis of Fundamental Mode State Machines (1/4)
    22. 14.17 Analysis of Fundamental Mode State Machines (2/4)
    23. 14.17 Analysis of Fundamental Mode State Machines (3/4)
    24. 14.17 Analysis of Fundamental Mode State Machines (4/4)
    25. Further Reading
    26. Problems (1/3)
    27. Problems (2/3)
    28. Problems (3/3)
  21. Chapter 15. The Pulse Mode Approach to Asynchronous FSM Design
    1. 15.1 Introduction
    2. 15.2 Pulse Mode Models and System Requirements
    3. 15.3 Other Characteristics of Pulse Mode FSMs
    4. 15.4 Design Examples (1/2)
    5. 15.4 Design Examples (2/2)
    6. 15.5 Analysis of Pulse Mode FSMs (1/2)
    7. 15.5 Analysis of Pulse Mode FSMs (2/2)
    8. 15.6 Perspective on the Pulse Mode Approach to FSM Design
    9. Further Reading
    10. Problems (1/2)
    11. Problems (2/2)
  22. Chapter 16. Externally Asynchronous/Internally Clocked (Pausable) Systems and Programmable Asynchronous Sequencers
    1. 16.1 Introduction
    2. 16.2 Externally Asynchronous/Internally Clocked Systems and Applications (1/4)
    3. 16.2 Externally Asynchronous/Internally Clocked Systems and Applications (2/4)
    4. 16.2 Externally Asynchronous/Internally Clocked Systems and Applications (3/4)
    5. 16.2 Externally Asynchronous/Internally Clocked Systems and Applications (4/4)
    6. 16.3 Asynchronous Programmable Sequencers (1/3)
    7. 16.3 Asynchronous Programmable Sequencers (2/3)
    8. 16.3 Asynchronous Programmable Sequencers (3/3)
    9. 16.4 One-Hot Programmable Asynchronous Sequencers (1/2)
    10. 16.4 One-Hot Programmable Asynchronous Sequencers (2/2)
    11. 16.5 Epilogue to Chapter 16
    12. Further Reading
    13. Problems
  23. A Other Transistor Logic Families
    1. A.1 Introduction to the Standard NMOS Logic Family
    2. A.2 Introduction to the TTL Logic Family
    3. A.3 Performance Characteristics of Important IC Logic Families
    4. Further Reading
  24. B Computer-Aided Engineering Tools
    1. B.1 Productivity Tools Bundled with this Text
    2. B.2 Other Productivity Tools
    3. Further Reading
  25. C IEEE Standard Symbols
    1. C.1 Gates
    2. C.2 Combinational Logic Devices
    3. C.3 Flip-Flops, Registers, and Counters
    4. Further Reading
  26. Index (1/5)
  27. Index (2/5)
  28. Index (3/5)
  29. Index (4/5)
  30. Index (5/5)

Product information

  • Title: Engineering Digital Design
  • Author(s): Richard F. Tinder
  • Release date: January 2000
  • Publisher(s): Academic Press
  • ISBN: 9780080505657