Embedded SoPC Design with Nios II Processor and Verilog Examples

CHAPTER 2

GATE-LEVEL COMBINATIONAL CIRCUIT

HDL (hardware description language) is used to describe and model digital systems. Verilog is one of the two major HDLs. In this chapter, we use a simple comparator to illustrate the skeleton of a Verilog program. The description uses only logical operators and represents a gate-level combinational circuit, which is composed of simple logic gates.

2.1 INTRODUCTION

Verilog is a hardware description language. It was developed in the mid-1980s and later transferred to the IEEE (Institute of Electrical and Electronics Engineers). The language is formally defined by IEEE Standard 1364. The standard was ratified in 1995 (referred to as Verilog-1995) and revised in 2001 (referred to as Verilog-2001). Many useful enhancements are added in the revised version. We use Verilog-2001 in this book.

Verilog is intended for describing and modeling a digital system at various levels and is an extremely complex language. The focus of this book is on hardware design rather than on the language. Instead of covering every aspect of Verilog, we introduce the key Verilog synthesis constructs by examining a collection of examples. Several advanced topics are examined further in Chapter 8 and detailed Verilog coverage may be explored through the sources listed in the bibliographic section at the end of the chapter.

Table 2.1 Truth table of 1-bit equality comparator

Although the syntax of Verilog is somewhat like that of the C language, its semantics (i.e., “meaning”) ...