Digital Integrated Circuit Design Using Verilog and Systemverilog

Chapter 2

Bottom-up design

Abstract

This chapter introduces the most fundamental building blocks of a Verilog design. It shows how components can be used to build up a design hierarchy and includes several constructs needed to create and verify a design.

Keywords

primitive

instance

instantiation

identifier

module

port

hierarchical design

timescale

Outline

 Primitive instantiation 11

 Designing with primitives 17

 Identifiers and escaped identifiers 21

 Bus declarations 22

 Design hierarchy and test fixtures 25

 Port association 33

 Timescales 36

 Summary 39

This chapter introduces the most fundamental building blocks of a Verilog design. It shows how components can be used to build up a design hierarchy and includes several constructs ...