24 Simulation with VHDL Testbenches
Chapter Contents
24.1 Synthesis versus Simulation
24.2 Testbench Types
24.3 Stimulus Generation
24.4 Testing the Stimuli
24.5 Testbench Template
24.6 Writing Type I Testbenches
24.7 Writing Type II Testbenches
24.8 Writing Type III Testbenches
24.9 Writing Type IV Testbenches
24.10 Exercises
Objective:
As mentioned earlier, VHDL allows circuit synthesis as well as circuit simulation. In the preceding chapters we concentrated on the former, so all VHDL statements and constructs employed there are synthesizable. We turn now to circuit simulation, where fundamental simulation procedures are introduced and then illustrated by means of complete examples. A brief tutorial on ModelSim, a popular simulator for ...
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