20 VHDL Design of Combinational Logic Circuits
Chapter Contents
20.2 BCD-to-SSD Conversion Function
20.3 Generic Multiplexer
20.5 Design of ROM Memory
20.6 Design of Synchronous RAM Memories
20.7 Exercises
Objective:
Combinational circuits were studied in Chapters 11 and 12, with logic circuits in the former and arithmetic circuits in the latter. The same division is made in the VHDL examples, with combinational logic designs presented in this chapter and combinational arithmetic designs illustrated in the next.
20.1 Generic Address Decoder
Address decoders were studied in Section 11.5. We illustrate now the design of the address decoder of Figure 20.1 (borrowed from Figure 11.7 ...
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