Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors

Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors

by Joseph Yiu
Released December 2020
Publisher(s): Newnes
ISBN: 9780128207369

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Book description

The Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors focuses on the Armv8-M architecture and the features that are available in the Cortex-M23 and Cortex- M33 processors.

This book covers a range of topics, including the instruction set, the programmer’s model, interrupt handling, OS support, and debug features. It demonstrates how to create software for the Cortex-M23 and Cortex-M33 processors by way of a range of examples, which will enable embedded software developers to understand the Armv8-M architecture.

This book also covers the TrustZone® technology in detail, including how it benefits security in IoT applications, its operations, how the technology affects the processor’s hardware (e.g., memory architecture, interrupt handling, etc.), and various other considerations in creating secure software.

  • Presents the first book on Armv8-M Architecture and its features as implemented in the Cortex-M23 and Cortex-M33 processors
  • Covers TrustZone technology in detail
  • Includes examples showing how to create software for Cortex-M23/M33 processors

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. Preface
  7. Contributing author: Paul Beckmann
  8. Acknowledgments
  9. Chapter 1: Introduction
    1. Abstract
    2. 1.1: Microcontrollers and processors
    3. 1.2: Classification of processors
    4. 1.3: The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture
    5. 1.4: Characteristics of the Cortex-M23 and Cortex-M33 processors
    6. 1.5: Why have two different processors?
    7. 1.6: Applications of the Cortex-M23 and Cortex-M33
    8. 1.7: Technical features
    9. 1.8: Comparison with previous generations of Cortex-M processors
    10. 1.9: Advantages of the Cortex-M23 and Cortex-M33 processors
    11. 1.10: Understanding microcontroller programming
    12. 1.11: Further reading
  10. Chapter 2: Getting started with Cortex-M programming
    1. Abstract
    2. 2.1: Overview
    3. 2.2: Some basic concepts
    4. 2.3: Introduction to Arm Cortex-M programming
    5. 2.4: Software development flow
    6. 2.5: Cortex Microcontroller Software Interface Standard (CMSIS)
    7. 2.6: Additional information on software development
  11. Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors
    1. Abstract
    2. 3.1: Design objectives of Cortex-M23 and Cortex-M33 processors
    3. 3.2: Block diagrams
    4. 3.3: Processor
    5. 3.4: Instruction set
    6. 3.5: Memory map
    7. 3.6: Bus interfaces
    8. 3.7: Memory protection
    9. 3.8: Interrupt and exception handling
    10. 3.9: Low power features
    11. 3.10: OS support features
    12. 3.11: Floating-point unit
    13. 3.12: Coprocessor interface and Arm Custom Instructions
    14. 3.13: Debug and trace support
    15. 3.14: Multicore system design support
    16. 3.15: Key feature enhancements in Cortex-M23 and Cortex-M33 processors
    17. 3.16: Compatibility with other Cortex-M processors
    18. 3.17: Processor configuration options
    19. 3.18: Introduction to TrustZone
    20. 3.19: Why TrustZone enables better security?
    21. 3.20: Firmware asset protection with eXecute-Only-Memory (XOM)
  12. Chapter 4: Architecture
    1. Abstract
    2. 4.1: Introduction to the Armv8-M architecture
    3. 4.2: Programmer's model
    4. 4.3: Memory system
    5. 4.4: Exceptions and Interrupts
    6. 4.5: Debug
    7. 4.6: Reset and reset sequence
    8. 4.7: Other related architecture information
  13. Chapter 5: Instruction set
    1. Abstract
    2. 5.1: Background
    3. 5.2: Instruction set features in various Cortex-M processors
    4. 5.3: Understanding the assembly language syntax
    5. 5.4: Use of a suffix in an instruction
    6. 5.5: Unified Assembly Language (UAL)
    7. 5.6: Instruction set—Moving data within the processors
    8. 5.7: Instruction set—Memory access
    9. 5.8: Instruction set—Arithmetic operations
    10. 5.9: Instruction set—Logic operations
    11. 5.10: Instruction set—Shift and rotate operations
    12. 5.11: Instruction set—Data conversions (extend and reverse ordering)
    13. 5.12: Instruction set—Bit field processing
    14. 5.13: Instruction set—Saturation operations
    15. 5.14: Instruction set—Program flow control
    16. 5.15: Instruction set—DSP extension
    17. 5.16: Instruction set—Floating point support instructions
    18. 5.17: Instruction set—Exception-related instructions
    19. 5.18: Instruction set—Sleep mode-related instructions
    20. 5.19: Instruction set—Memory barrier instructions
    21. 5.20: Instruction set—TrustZone support instructions
    22. 5.21: Instruction set—Coprocessor and Arm custom instructions support
    23. 5.22: Instruction set—Other functions
    24. 5.23: Accessing special registers with the CMSIS-CORE
  14. Chapter 6: Memory system
    1. Abstract
    2. 6.1: Overview of the memory system
    3. 6.2: Memory map
    4. 6.3: Memory types and memory attributes
    5. 6.4: Access permission management
    6. 6.5: Memory endianness
    7. 6.6: Data alignment and unaligned data access support
    8. 6.7: Exclusive access support
    9. 6.8: Memory ordering and memory barrier instructions
    10. 6.9: Bus wait state and error support
    11. 6.10: Single-cycle I/O port—Cortex-M23 only
    12. 6.11: Memory systems in microcontrollers
    13. 6.12: Software considerations
  15. Chapter 7: TrustZone support in the memory system
    1. Abstract
    2. 7.1: Overview
    3. 7.2: SAU and IDAU
    4. 7.3: Banked and nonbanked registers
    5. 7.4: Test Target (TT) instructions and region ID numbers
    6. 7.5: Memory protection controller and peripheral protection controller
    7. 7.6: Security aware peripherals
  16. Chapter 8: Exceptions and interrupts—Architecture overview
    1. Abstract
    2. 8.1: Overview of exceptions and interrupts
    3. 8.2: Exception types
    4. 8.3: Overview of interrupts and exceptions management
    5. 8.4: Exception sequence introduction
    6. 8.5: Definitions of exception priority levels
    7. 8.6: Vector table and vector table offset register (VTOR)
    8. 8.7: Interrupt input and pending behaviors
    9. 8.8: Target states of exceptions and interrupts in TrustZone systems
    10. 8.9: Stack frames
    11. 8.10: EXC_RETURN
    12. 8.11: Classification of synchronous and asynchronous exceptions
  17. Chapter 9: Management of exceptions and interrupts
    1. Abstract
    2. 9.1: Overview of exception and interrupt management
    3. 9.2: Details of the NVIC registers for interrupt management
    4. 9.3: Details of SCB registers for system exception management
    5. 9.4: Details of special registers for exception or interrupt masking
    6. 9.5: Vector table definition in programming
    7. 9.6: Interrupt latency and exception handling optimizations
    8. 9.7: Tips and hints
  18. Chapter 10: Low power and system control features
    1. Abstract
    2. 10.1: The quest for low power
    3. 10.2: Low power features in the Cortex-M23 and Cortex-M33 processors
    4. 10.3: More on WFI, WFE, and SEV instructions
    5. 10.4: Developing low power applications
    6. 10.5: System Control Block (SCB) and system control features
    7. 10.6: Auxiliary Control Register
    8. 10.7: Other registers in the System Control Block
  19. Chapter 11: OS support features
    1. Abstract
    2. 11.1: Overview of the OS support features
    3. 11.2: SysTick timer
    4. 11.3: Banked stack pointers
    5. 11.4: Stack limit checking
    6. 11.5: SVCall and PendSV exceptions
    7. 11.6: Unprivileged execution level and the Memory Protection Unit (MPU)
    8. 11.7: Exclusive access
    9. 11.8: How should an RTOS run in a TrustZone environment?
    10. 11.9: Concepts of RTOS operations in Cortex-M processors
  20. Chapter 12: Memory Protection Unit (MPU)
    1. Abstract
    2. 12.1: Overview of the MPU
    3. 12.2: MPU registers
    4. 12.3: Configuration of the MPU
    5. 12.4: TrustZone and MPU
    6. 12.5: Key differences between the MPU in Armv8-M architecture and the architecture of the previous generations
  21. Chapter 13: Fault exceptions and fault handling
    1. Abstract
    2. 13.1: Overview
    3. 13.2: Cause of faults
    4. 13.3: Enabling fault exceptions
    5. 13.4: Fault handler designs considerations
    6. 13.5: Fault status and other information
    7. 13.6: Lockup
    8. 13.7: Analysis of fault events
    9. 13.8: Stack trace
    10. 13.9: Fault handler to extract stack frame and display fault status
  22. Chapter 14: The Floating-Point Unit (FPU) in the Cortex-M33 processor
    1. Abstract
    2. 14.1: Floating-point data
    3. 14.2: Cortex-M33 Floating-point Unit (FPU)
    4. 14.3: Key differences between the FPUs of the Cortex-M33 FPU and the Cortex-M4
    5. 14.4: Lazy stacking in details
    6. 14.5: Using the FPU
    7. 14.6: Floating-point exceptions
    8. 14.7: Hints and tips
  23. Chapter 15: Coprocessor interface and Arm Custom Instructions
    1. Abstract
    2. 15.1: Overview
    3. 15.2: Overview of the architecture
    4. 15.3: Accessing coprocessor instructions via intrinsic functions in C
    5. 15.4: Accessing Arm Custom Instructions via the intrinsic functions in C
    6. 15.5: Software steps to take when enabling the coprocessor and the Arm Custom Instructions
    7. 15.6: Coprocessor power control
    8. 15.7: Hints and tips
  24. Chapter 16: Introduction to the debug and trace features
    1. Abstract
    2. 16.1: Introduction
    3. 16.2: Debug architecture details
    4. 16.3: An introduction to debug components
    5. 16.4: Starting a debug session
    6. 16.5: Flash memory programming support
    7. 16.6: Software design considerations
  25. Chapter 17: Software development
    1. Abstract
    2. 17.1: Introduction
    3. 17.2: Getting started with the Keil Microcontroller Development Kit (MDK)
    4. 17.3: Procedure Call Standard for the Arm Architecture
    5. 17.4: Software scenarios
  26. Chapter 18: Secure software development
    1. Abstract
    2. 18.1: Overview of Secure software development
    3. 18.2: TrustZone technical details
    4. 18.3: Secure software development
    5. 18.4: Creating a Secure project in Keil MDK
    6. 18.5: CMSE support in other toolchains
    7. 18.6: Secure software design considerations
  27. Chapter 19: Digital signal processing on the cortex-M33 processor
    1. Abstract
    2. 19.1: DSP on a microcontroller?
    3. 19.2: Why use a Cortex-M processor for a DSP application?
    4. 19.3: Dot product example
    5. 19.4: Getting more performance by utilizing the SIMD instructions
    6. 19.5: Dealing with overflows
    7. 19.6: Introduction to data types for signal processing
    8. 19.7: Cortex-M33 DSP instructions
    9. 19.8: Writing optimized DSP code for the Cortex-M33 processor
  28. Chapter 20: Using the Arm CMSIS-DSP library
    1. Abstract
    2. 20.1: Overview of the library
    3. 20.2: Function naming convention
    4. 20.3: Getting help
    5. 20.4: Example 1—DTMF demodulation
    6. 20.5: Example 2—Least squares motion tracking
    7. 20.6: Example 3—Real-time filter design
    8. 20.7: How to determine the implemented instruction set features in a Cortex-M33 based system
  29. Chapter 21: Advanced topics
    1. Abstract
    2. 21.1: Further information on stack memory protection
    3. 21.2: Semaphores, load-acquire and store-release instructions
    4. 21.3: Unprivileged interrupt handler
    5. 21.4: Re-entrant interrupt handler
    6. 21.5: Software optimization topics
  30. Chapter 22: Introduction to IoT security and the PSA Certified™ framework
    1. Abstract
    2. 22.1: From processor architecture to IoT security
    3. 22.2: Introduction of PSA Certified
    4. 22.3: The Trusted Firmware-M (TF-M) project
    5. 22.4: Additional information
  31. Index

Product information

  • Title: Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors
  • Author(s): Joseph Yiu
  • Release date: December 2020
  • Publisher(s): Newnes
  • ISBN: 9780128207369